UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 491

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Master operation in multi-master system
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period
1
No
of one frame). If the SDAA0 pin is constantly at low level, decide whether to release the I
and SDAA0 pins = high level) in conformance with the specifications of the product that is communicating.
ACKE0 = WTIM0 = SPIE0 = 1
Setting STCEN and IICRSV
IICACTL0
IICACTL0
Checking bus status
IICWL, IICWH
Enables reserving
interrupt occurs?
Master operation
communication.
IICAF0
SVA0
IICRSV = 0?
Setting port
Setting port
SPD0 = 1?
SPIE0 = 1
IICE0 = 1
INTIICA0
START
starts?
A
0XX111XXB
1XX111XXB
Yes
Yes
Yes
Yes
(Communication start request)
XXH
0XH
Bus status is
being checked.
Waiting to be specified as a slave by other master
Waiting for a communication start request (depends on user program)
Figure 15-31. Master Operation in Multi-Master System (1/3)
XXH
Note
Disables reserving
communication.
(No communication start request)
No
No
No
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Releases the bus for a specific period.
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (9) Port mode register 6 (PM6)).
Slave operation
Set the port from input mode to output mode and enable the output of the I
(see 15.3 (9) Port mode register 6 (PM6)).
B
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
STCEN = 1?
Yes
interrupt occurs?
Slave operation
SPIE0 = 0
INTIICA0
Yes
No
Waits for a communication request.
No
interrupt occurs?
SPD0 = 1?
SPT0 = 1
INTIICA0
Yes
Yes
2
C bus
No
No
Waits for detection
of the stop condition.
Prepares for starting
communication
(generates a stop condition).
Slave operation
2
C bus (SCLA0
491