UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 446

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) Permissible baud rate range during reception
446
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
As shown in Figure 14-26, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
Maximum permissible
Minimum permissible
FL = (Brate)
Data frame length
Brate: Baud rate of UART6
k:
FL:
Margin of latch timing: 2 clocks
data frame length
data frame length
using the calculation expression shown below.
of UART6
Set value of BRGC6
1-bit data length
1
Figure 14-26. Permissible Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
CHAPTER 14 SERIAL INTERFACE UART6
Preliminary User’s Manual U19111EJ2V1UD
Bit 0
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
1 data frame (11
FLmin
FLmax
Bit 7
Bit 7
FL)
Bit 7
Parity bit
Parity bit
Parity bit
Stop bit
Stop bit
Stop bit