UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 649

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
<R>
Address: 0081H/1081H
Address: 0082H/1082H
Notes 1.
Caution Be sure to clear bits 7 to 1 to “0”.
Note Set a value that is the same as that of 0082H to 1082H because 0082H and 1082H are switched during the
Caution Be sure to clear bits 7 to 1 to “0”.
boot swap operation.
2.
R4M8MSEL
LVISTART
LVISTART can only be written by using a dedicated flash memory programmer. It cannot be set during
self-programming or boot swap operation during self-programming. However, because 0080H and
1080H are switched during the boot swap operation, set a value that is the same as that of 0080H to
1080H.
To change the setting for the LVI default start, set the value to 0081H again after batch erasure (chip
erasure) of the flash memory. The setting cannot be changed after the memory of the specified block
is erased.
7
0
0
1
7
0
0
1
Notes 1, 2
Note
LVI is OFF by default upon reset release or upon power application (LVI default start function
stopped)
LVI is ON by default upon reset release or upon power application (LVI default start function
enabled)
8 MHz (TYP.)
4 MHz (TYP.)
6
0
6
0
Figure 24-1. Format of Option Byte (2/3)
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 24 OPTION BYTE
5
0
5
0
Internal high-speed oscillation clock frequency selection
LVI default start operation control
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
R4M8MSEL
LVISTART
0
0
649

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