UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 94

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.4.4 Short direct addressing
94
Effective address
[Function]
[Operand format]
[Description example]
[Illustration]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special
function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] shown below.
LB1 EQU 0FE30H ; Defines FE30H by LB1.
MOV LB1, A
When 8-bit immediate data is 20H to FFH,
When 8-bit immediate data is 00H to 1FH,
:
saddr
saddrp
Identifier
15
7
1
Operation code
1
; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to
1
that address
saddr-offset
Immediate data that indicate label or FE20H to FF1FH
Immediate data that indicate label or FE20H to FF1FH (even address only)
OP code
1
1
1
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 3 CPU ARCHITECTURE
1
1
0
0
8 7
1
0
= 1
= 0
1
1
1
1
0
0
Description
0
0
1
0
0
0
OP code
30H (saddr-offset)
0
Short direct memory