UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 183

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UPD78F0550MA-FAA-AX

Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0550MA-FAA-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(7) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1
clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock,
the X1 clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Address: FFA3H
Symbol
OSTC
Figure 5-10. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
MOST11
7
0
1
1
1
1
1
After reset: 00H
2. The oscillation stabilization time counter counts up to the oscillation
3. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
MOST13
remain 1.
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
clock oscillation starts (“a” below).
6
0
0
1
1
1
1
X1 pin voltage
waveform
Desired OSTC oscillation stabilization time
set by OSTS
R
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 5 CLOCK GENERATOR
MOST14
5
0
0
0
1
1
1
STOP mode release
MOST11
MOST15
4
0
0
0
1
1
a
MOST13
MOST16
3
0
0
0
0
1
2
2
2
2
2
11
13
14
15
16
MOST14
Oscillation stabilization time status
/f
/f
/f
/f
/f
X
X
X
X
X
2
min.
min.
min.
min.
min.
Oscillation stabilization time
MOST15
1
204.8 s min.
819.2 s min.
1.64 ms min.
3.27 ms min.
6.55 ms min.
f
X
= 10 MHz
MOST16
0
183

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