UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 476

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5.8 Interrupt request (INTIICA0) generation timing and wait control
generated and the corresponding wait control, as shown in Table 15-2.
476
The setting of bit 3 (WTIM0) of IICA control register 0 (IICACTL0) determines the timing by which INTIICA0 is
WTIM0
Notes 1. The slave device’s INTIICA0 signal and wait period occurs at the falling edge of the ninth clock only
Remark
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
(5) Stop condition detection
0
1
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
The four wait cancellation methods are as follows.
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
INTIICA0 is generated when a stop condition is detected (only when SPIE0 = 1).
Writing data to IICA shift register (IICA)
Setting bit 5 (WREL0) of IICA control register 0 (IICACTL0) (canceling wait)
Setting bit 1 (STT0) of IICACTL0 register (generating start condition)
Setting bit 0 (SPT0) of IICACTL0 register (generating stop condition)
Note Master only.
2. If the received address does not match the contents of the slave address register 0 (SVA0) and
when there is a match with the address set to the slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICACTL0’s bit 2 (ACKE0). For a slave
device that has received an extension code, INTIICA0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICA0 is generated at the falling edge of the 9th
clock, but wait does not occur.
extension code is not received, neither INTIICA0 nor a wait occurs.
The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
Address
9
9
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Table 15-2. INTIICA0 Generation Timing and Wait Control
Data Reception
Notes 1 and 2 above, regardless of the WTIM0 bit.
the WTIM0 bit.
Interrupt and wait timing are determined depending on the conditions described in
8
9
Note 2
Note 2
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
Data Transmission
8
9
Note 2
Note 2
Address
9
9
During Master Device Operation
Note
Note
Data Reception
8
9
Data Transmission
8
9