UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 422
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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(5) Baud rate generator control register 6 (BRGC6)
422
Address: FF57H After reset: FFH R/W
BRGC6
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
Remarks 1. f
Symbol
This register sets the division value of the 8-bit counter of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation
2. The baud rate is the output clock of the 8-bit counter divided by 2.
2. k: Value set by MDL67 to MDL60 bits (k = 4, 5, 6, ..., 255)
3.
MDL67
MDL67
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
7
0
0
0
0
1
1
1
1
MDL67 to MDL60 bits.
XCLK6
: Don’t care
Figure 14-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
MDL66
MDL66
: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
6
0
0
0
0
1
1
1
1
MDL65
MDL65
5
0
0
0
0
1
1
1
1
CHAPTER 14 SERIAL INTERFACE UART6
MDL64
MDL64
Preliminary User’s Manual U19111EJ2V1UD
4
0
0
0
0
1
1
1
1
MDL63
MDL63
3
0
0
0
0
1
1
1
1
MDL62
MDL62
2
0
1
1
1
1
1
1
1
MDL61
MDL61
1
0
0
1
0
0
1
1
MDL60
MDL60
0
0
1
0
0
1
0
1
252
253
254
255
k
4
5
6
Setting prohibited
f
f
f
f
f
f
f
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
Output clock selection of
/4
/5
/6
/252
/253
/254
/255
8-bit counter
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