UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 378

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(3) 8-bit A/D conversion result register L (ADCRL)
(4) 8-bit A/D conversion result register H (ADCRH)
378
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel
This register is an 8-bit register that stores the A/D conversion result. The lower 8 bits of 10-bit resolution are
stored.
ADCRL can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are
stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
2. If data is read from ADCRL, a wait cycle is generated. Do not read data from ADCRL when
2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when
Address: FF08H
Address: FF0DH
ADCRH
Symbol
ADCRL
Symbol
specification register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the
contents of ADCRL may become undefined. Read the conversion result following conversion
completion before writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the
above may cause an incorrect conversion result to be read.
the peripheral hardware clock (f
FOR WAIT.
specification register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the
contents of ADCRH may become undefined.
conversion completion before writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other
than the above may cause an incorrect conversion result to be read.
the peripheral hardware clock (f
FOR WAIT.
Figure 12-6. Format of 8-Bit A/D Conversion Result Register L (ADCRL)
Figure 12-7. Format of 8-Bit A/D Conversion Result Register (ADCRH)
7
7
After reset: 00H
After reset: 00H
6
6
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 12 A/D CONVERTER
5
5
R
R
PRS
PRS
) is stopped. For details, refer to CHAPTER 31 CAUTIONS
) is stopped. For details, refer to CHAPTER 31 CAUTIONS
4
4
3
3
Read the conversion result following
2
2
1
1
0
0