UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 346
UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Address: FFB0H, FFB1H
Address: FFB2H
RSUBC
Symbol
(5) Sub-count register (RSUBC)
(6) Second count register (SEC)
Symbol
SEC
The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It
takes a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz.
RSUBC can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Cautions 1. When a correction is made by using the SUBCUD register, the value may become 8000H
The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
seconds.
It counts up when the sub-counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Set a decimal value of 00 to 59 to this register in BCD code. If a value outside this range is set, the
register value returns to the normal value after 1 period.
SEC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
15
2. This register is also cleared by reset effected by writing the second count register.
3. The value read from this register is not guaranteed if it is read during operation, because
14
After reset: 00H
7
0
or more.
a value that is changing is read.
13
After reset: 0000H
SEC40
Figure 10-7. Format of Second Count Register (SEC)
Figure 10-6. Format of Sub-Count Register (RSUBC)
12
6
FFB1H
R/W
11
CHAPTER 10 REAL-TIME COUNTER
Preliminary User’s Manual U19111EJ2V1UD
SEC20
5
10
R
9
SEC10
4
8
7
SEC8
3
6
5
SEC4
2
4
FFB0H
3
SEC2
1
2
1
SEC1
0
0
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