UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 68

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

68
Data memory
space
Figure 3-2. Memory Map ( PD78F0551, 78F0556, 78F0561, 78F0566, 78F0571, 78F0576, 78F0581, 78F0586)
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
Program
memory space
2. Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6 Security
refer to Table 3-2
Memory.
When boot swap is used:
Settings).
FEDFH
FCFFH
FFFFH
FEFFH
FEE0H
FD00H
1FFFH
FF00H
2000H
0000H
Special function registers
Internal high-speed RAM
General-purpose
32
registers
Flash memory
8192
512
256
Reserved
1 B F F H
1 F F F H
1 C 0 0 H
0 7 F F H
0 3 F F H
0 8 0 0 H
0 4 0 0 H
0 0 0 0 H
8 bits
(SFR)
Correspondence Between Address Values and Block Numbers in Flash
8 bits
8 bits
8 bits
Preliminary User’s Manual U19111EJ2V1UD
CHAPTER 3 CPU ARCHITECTURE
IDs to 0085H to 008EH.
Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
Block 07H
Block 01H
Block 00H
1FFFH
0FFFH
108EH
07FFH
008EH
108FH
1085H
1084H
1080H
107FH
1000H
0800H
008FH
0085H
0084H
0080H
007FH
0040H
003FH
0000H
1 KB
On-chip debug security
Option byte area
On-chip debug security
Option byte area
ID setting area
ID setting area
CALLF entry area
CALLT table area
Vector table area
Program area
Program area
Program area
1905
2048
10
5
10
64
64
5
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
Note 1
Note 1
Note 1
Note 1
1FFFH
Boot cluster 0
Boot cluster 1
Note 2