UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 509
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UPD78F0550MA-FAA-AX
Manufacturer Part Number
UPD78F0550MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet
1.UPD78F0550MA-FAA-AX.pdf
(734 pages)
Specifications of UPD78F0550MA-FAA-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
10MHz
Number Of I /o
12
Core Processor
78K/0
Program Memory Type
FLASH
Ram Size
384 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
LVD, POR, PWM, WDT
Connectivity
I²C, LIN, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
Renesas
Quantity:
800
Part Number:
UPD78F0550MA-FAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 509 of 734
- Download datasheet (4Mb)
(4) Operation without communication
Remark
(5) Arbitration loss operation (operation as slave after arbitration loss)
Remark
ST
1: IICAS0 = 00000001B
ST
1: IICAS0 = 0101×110B
2: IICAS0 = 0001×000B
3: IICAS0 = 0001×000B
4: IICAS0 = 00000001B
(a) Start ~ Code ~ Data ~ Data ~ Stop
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIICA0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data
AD6 to AD0 R/W ACK
AD6 to AD0 R/W ACK
(i) When WTIM0 = 0
×:
: Generated only when SPIE0 = 1
: Always generated
: Generated only when SPIE0 = 1
Don’t care
1
D7 to D0
D7 to D0
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
ACK
ACK
2
D7 to D0
D7 to D0
ACK
ACK
3
SP
SP
4
1
509
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