UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 542

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(2) Communication operation
542
<1> Low level input to the SSI11 pin
<2> High level input to the SSI11 pin
<3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low
<4> A high level is input to the SSI11 pin during transmission/reception or reception
Remarks 1. 78K0/KB2-L: n = 0
In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or
received in synchronization with the serial clock.
Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1.
Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition,
data can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0.
Reception is started when data is read from serial I/O shift register 1n (SIO1n).
However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in
the slave mode.
After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data
has been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared
to 0. Then the next communication is enabled.
Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial
level is input to the SSI11 pin
Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read.
Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read,
transmission/reception or reception will not be started.
Transmission/reception or reception is started.
Transmission/reception or reception is suspended.
2. The SSI11 pin is available only in 48-pin products of 78K0/KC2-L.
2. When using serial interface CSI11, wait for the duration of at least one clock before the
78K0/KC2-L: n = 0, 1
communication).
clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise,
malfunctioning may occur.
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
Preliminary User’s Manual U19111EJ2V1UD