UPD78F0550MA-FAA-AX Renesas Electronics America, UPD78F0550MA-FAA-AX Datasheet - Page 474

• Manufacturer Part Number: UPD78F0550MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0550MA-FAA-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 12
• Core Processor: 78K/0
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Connectivity: I²C, LIN, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(IICACTL0).
written to the IICA shift register (IICA), and the transmitting side cancels the wait state when data is written to IICA.
474
Transfer lines
(2) When master and slave devices both have a nine-clock wait
Remark
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IICA control register 0
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICACTL0 is set to 1 or when FFH is
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICACTL0 to 1
• By setting bit 0 (SPT0) of IICACTL0 to 1
Master
Slave
(master transmits, slave receives, and ACKE0 = 1)
ACKE0: Bit 2 of IICA control register 0 (IICACTL0)
WREL0: Bit 5 of IICA control register 0 (IICACTL0)
ACKE0
SDAA0
SCLA0
SCLA0
SCLA0
IICA
IICA
H
Generate according to previously set ACKE0 value
D2
6
6
Master and slave both wait
after output of ninth clock
D1
7
7
CHAPTER 15 SERIAL INTERFACE IICA
Preliminary User’s Manual U19111EJ2V1UD
D0
8
8
Figure 15-21. Wait (2/2)
ACK
9
9
Wait from
master and
slave
Wait from slave
IICA data write (cancel wait)
1
D7
1
FFH is written to IICA or WREL0 is set to 1
D6
2
2
D5
3
3