PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 10

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PI7C9X110

Manufacturer Part Number
PI7C9X110
Description
Pcie-to-pci Reversible Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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0
8
9
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14
15
16
11.1
11.2
14.1
14.2
14.3
14.4
14.5
7.6.10
7.6.11
7.6.12
7.6.13
7.6.14
7.6.15
7.6.16
7.6.17
7.6.18
7.6.19
7.6.20
7.6.21
7.6.22
7.6.23
7.6.24
7.6.25
7.6.26
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7.6.31
7.6.32
7.6.33
7.6.34
7.6.35
7.6.36
7.6.37
GPIO PINS AND SM BUS ADDRESS..................................................................................... 133
CLOCK SCHEME ..................................................................................................................... 133
Pericom Semiconductor
INTERRUPTS......................................................................................................................... 133
EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS ........................... 134
HOT PLUG OPERATION .................................................................................................... 134
RESET SCHEME................................................................................................................... 135
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ....................................................... 136
POWER MANAGEMENT .................................................................................................... 140
ELECTRICAL AND TIMING SPECIFICATIONS........................................................... 141
EEPROM (I2C) INTERFACE........................................................................................................................... 134
SYSTEM MANAGEMENT BUS ..................................................................................................................... 134
INSTRUCTION REGISTER ............................................................................................................................ 136
BYPASS REGISTER........................................................................................................................................ 136
DEVICE ID REGISTER ................................................................................................................................... 136
BOUNDARY SCAN REGISTER ..................................................................................................................... 137
JTAG BOUNDARY SCAN REGISTER ORDER ............................................................................................ 137
RESERVED REGISTERS – OFFSET 03Ch TO 04Ch ........................................................................ 126
LOOKUP TABLE OFFSET – OFFSET 050h ..................................................................................... 126
LOOKUP TABLE DATA – OFFSET 054h.......................................................................................... 126
UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER – OFFSET 058h ............................ 127
UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER – OFFSET 05Ch............................ 127
UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER – OFFSET 060h ................................... 128
UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER – OFFSET 064h ................................... 128
RESERVED REGISTER – OFFSET 068C .......................................................................................... 128
PRIMARY CLEAR IRQ REGISTER – OFFSET 070h......................................................................... 128
SECONDARY CLEAR IRQ REGISTER – OFFSET 070h................................................................... 128
PRIMARY SET IRQ REGISTER – OFFSET 074h .............................................................................. 129
SECONDARY SET IRQ REGISTER – OFFSET 074h ........................................................................ 129
PRIMARY CLEAR IRQ MASK REGISTER – OFFSET 078h ............................................................. 129
SECONDARY CLEAR IRQ MASK REGISTER – OFFSET 078h ....................................................... 129
PRIMARY SET IRQ MASK REGISTER – OFFSET 07Ch .................................................................. 130
SECONDARY SET IRQ MASK REGISTER – OFFSET 07Ch ............................................................ 130
RESERVED REGISTERS – OFFSET 080h TO 09Ch ......................................................................... 130
SCRATCHPAD 0 REGISTER – OFFSET 0A0h.................................................................................. 130
SCRATCHPAD 1 REGISTER – OFFSET 0A4h.................................................................................. 130
SCRATCHPAD 2 REGISTER – OFFSET 0A8h.................................................................................. 131
SCRATCHPAD 3 REGISTER – OFFSET 0ACh ................................................................................. 131
SCRATCHPAD 4 REGISTER – OFFSET 0B0h.................................................................................. 131
SCRATCHPAD 5 REGISTER – OFFSET 0B4h.................................................................................. 131
SCRATCHPAD 6 REGISTER – OFFSET 0B8h.................................................................................. 131
SCRATCHPAD 7 REGISTER – OFFSET 0BCh ................................................................................. 132
RESERVED REGISTERS – OFFSET 0C0h TO 0FCh........................................................................ 132
LOOKUP TABLE REGISTERS – OFFSET 100h TO 1FCh ............................................................... 132
RESERVED REGISTERS – OFFSET 200h TO FFCh ........................................................................ 132
Page 10 of 145
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110

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