PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 31

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.3
Note 5: Read access only.
Table 7-3 Control and Status Register (CSR) Map (000h – FFFh)
Pericom Semiconductor
CONTROL AND STATUS REGISTER MAP
Primary Bus
Configuration Access
for both Transparent
and Non-Transparent
mode, or Secondary
Bus Configuration
Access for Transparent
Mode
133h – 130h
137h – 134h
13Bh – 138h
14Bh – 13Ch
14Fh – 14Ch
153h – 150h
157h – 154h
15Bh – 158h
15Fh – 15Ch
163h – 160h
167h – 164h
16Bh – 168h
2FFh – 170h
303h – 300h
307h – 304h
30Fh – 308h
310h
4FFh – 314h
503h – 500h
504h
50Fh – 505h
510h
FFFh – 514h
PCI Express / PCI
Memory Offset
007h – 000h
00Bh – 008h
00Fh – 00Ch
013h – 010h
017h – 014h
01Bh – 018h
02Fh – 01Ch
Secondary Bus
Configuration Access
for Non-Transparent
Mode Only
133h – 130h
137h – 134h
13Bh – 138h
14Bh – 13Ch
14Fh – 14Ch
153h – 150h
157h – 154h
15Bh – 158h
15Fh – 15Ch
163h – 160h
167h – 164h
16Bh – 168h
2FFh – 170h
503h – 500h
507h – 504h
50Fh – 508h
510h
4FFh – 314h
303h – 300h
304h
30Fh – 305h
310h
FFFh – 514h
SM Bus Offset
207h – 200h
20Bh – 208h
20Fh – 20Ch
213h – 210h
217h – 214h
21Bh – 218h
22Fh – 21Ch
Page 31 of 145
VC Capability
Port VC Capability 1
VC0 Resource Control
Transparent Mode
(type1)
Secondary
Uncorrectable Error
Mask
Secondary
Uncorrectable Severity
Secondary AER
Control
Secondary Header Log
Register
Reserved
Port VC Capability 2
Port VC Status and
Control
VC0 Resource
Capability
VC0 Resource Status
Reserved
Reserved
Extended GPI/GPO
Data and Control
Reserved
Replay and
Acknowledge Latency
Timer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register Name
Reserved
Downstream Memory
2 Translated Base
Downstream Memory
2 Setup
Downstream Memory
3 Translated Base
Downstream Memory
3 Setup
Downstream Memory
3 Upper 32-bit Setup
Reserved
Non-Transparent
Mode (Type0)
Secondary
Uncorrectable Error
Mask
Secondary
Uncorrectable Severity
Secondary AER
Control
Secondary Header Log
Register
Reserved
VC Capability
Port VC Capability 1
Port VC Capability 2
Port VC Status and
Control
VC0 Resource
Capability
VC0 Resource Control
VC0 Resource Status
Reserved
Reserved
Extended GPI/GPO
Data and Control
Reserved
Replay and
Acknowledge Latency
Timer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reset Value
0
XXXX_XXXXh
0000_0000h
XXXX_XXXXh
0000_0000h
0000_0000h
0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
EEPROM
(I2C)
Access
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
No
No
No
No
No
No
EEPROM
(I2C)
Access
No
No
Yes
No
Yes
Yes
No
PI7C9X110
SM Bus
Access
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
No
No
No
No
No
No
SM Bus
Access
Yes
Yes
Yes
Yes
Yes
Yes
Yes