PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 6

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

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Pericom Semiconductor
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 58
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 58
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h ................................................................... 58
DEVICE CAPABILITY REGISTER – OFFSET B4h............................................................................. 58
DEVICE CONTROL REGISTER – OFFSET B8h................................................................................. 59
DEVICE STATUS REGISTER – OFFSET B8h..................................................................................... 60
LINK CAPABILITY REGISTER – OFFSET BCh ................................................................................. 60
LINK CONTROL REGISTER – OFFSET C0h...................................................................................... 61
LINK STATUS REGISTER – OFFSET C0h.......................................................................................... 61
SLOT CAPABILITY REGISTER – OFFSET C4h ................................................................................. 62
SLOT CONTROL REGISTER – OFFSET C8h ..................................................................................... 62
SLOT STATUS REGISTER – OFFSET C8h ......................................................................................... 63
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh..................................................................... 63
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ..................................................................... 63
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ..................................................................... 63
HOT SWAP SWITCH DEBOUNCE COUNTER – OFFSET D4h......................................................... 65
CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................... 65
NEXT POINTER REGISTER – OFFSET D8h ...................................................................................... 65
VPD REGISTER – OFFSET D8h ......................................................................................................... 65
VPD DATA REGISTER – OFFSET DCh.............................................................................................. 65
RESERVED REGISTERS – OFFSET E0h – ECh ................................................................................. 66
MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h............................................................... 66
NEXT CAPABILITIES POINTER REGISTER – F0h............................................................................ 66
MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................. 66
MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................. 66
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h................................................................. 66
MESSAGE DATA REGISTER – OFFSET FCh..................................................................................... 67
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................. 67
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................. 67
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ................................................................ 67
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................... 67
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...................................................... 67
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch............................................... 68
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h......................................................... 68
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ............................................................ 68
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h........................ 69
HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................... 69
HEADER LOG REGISTER 2 – OFFSET 120h..................................................................................... 69
HEADER LOG REGISTER 3 – OFFSET 124h..................................................................................... 69
HEADER LOG REGISTER 4 – OFFSET 128h..................................................................................... 69
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ........................... 69
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................... 70
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ........................ 70
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h.......................... 71
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 71
RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 71
VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 71
VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 71
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 72
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 72
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 72
PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 72
Page 6 of 145
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110