PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 83

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.26 CHIP CONTROL 0 REGISTER – OFFSET 40h
Pericom Semiconductor
BIT
9:8
10
11
14:12
BIT
15
16
18:17
19
FUNCTION
PCI Read Prefetch Mode
PCI Special Delayed Read
Mode Enable
Reserved
Maximum Memory Read
Byte Count
FUNCTION
Flow Control Update
Control
PCI Retry Counter Status
PCI Retry Counter Control
PCI Discard Timer Disable
TYPE
TYPE
RWC
RW
RW
RW
RW
RW
RW
RO
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DESCRIPTION
00: One cache line prefetch if memory read address is in prefetchable range
at PCI interface
01: Reserved
10: Full prefetch if memory read address is in prefetchable range at PCI
interface
11: Disconnect on the first DWORD
Reset to 00
0: Retry any master at PCI bus that repeats its transaction with command
code changes.
1: Allows any master at PCI bus to change memory command code (MR,
MRL, MRM) after it has received a retry. The PI7C9X110 will complete the
memory read transaction and return data back to the master if the address and
byte enables are the same.
Reset to 0
Reset to 0
Maximum byte count is used by the PI7C9X110 when generating memory
read requests on the PCIe link in response to a memory read initiated on the
PCI bus and bit [9:8], bit [7:6], and bit [5:4] are set to “full prefetch”.
000: 512 bytes (default)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
101: 2048 bytes
110: 4096 bytes
111: 512 bytes
Reset to 000
DESCRIPTION
0: Flow control is updated for every two credits available
1: Flow control is updated for every on credit available
Reset to 0
0: The PCI retry counter has not expired since the last reset
1: The PCI retry counter has expired since the last reset
Reset to 0
00: No expiration limit
01: Allow 256 retries before expiration
10: Allow 64K retries before expiration
11: Allow 2G retries before expiration
Reset to 00
0: Enable the PCI discard timer in conjunction with bit [27] offset 3Ch
(bridge control register)
1: Disable the PCI discard timer in conjunction with bit [27] offset 3Ch
(bridge control register)
Reset to 0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110