PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 65

no-image

PI7C9X110

Manufacturer Part Number
PI7C9X110
Description
Pcie-to-pci Reversible Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C9X110BNB
Manufacturer:
LATTICE
Quantity:
308
Part Number:
PI7C9X110BNB
Manufacturer:
PERICOM
Quantity:
20 000
Part Number:
PI7C9X110BNBE
Manufacturer:
PLX
Quantity:
1 238
Part Number:
PI7C9X110BNBE
Manufacturer:
PERICOM31
Quantity:
193
Part Number:
PI7C9X110BNBE
Manufacturer:
Pericom
Quantity:
10 000
Part Number:
PI7C9X110BNBE
Manufacturer:
PERICOM
Quantity:
20 000
Part Number:
PI7C9X110BNBE
0
7.4.82 HOT SWAP SWITCH DEBOUNCE COUNTER – OFFSET D4h
7.4.83 CAPABILITY ID REGISTER – OFFSET D8h
7.4.84 NEXT POINTER REGISTER – OFFSET D8h
7.4.85 VPD REGISTER – OFFSET D8h
7.4.86 VPD DATA REGISTER – OFFSET DCh
Pericom Semiconductor
BIT
31:24
BIT
7:0
BIT
15:8
BIT
17:16
23:18
30:24
31
BIT
31:0
FUNCTION
Hot Swap Debounce Counter
FUNCTION
Capability ID for VPD
Register
FUNCTION
Next Pointer
FUNCTION
Reserved
VPD Address for
Read/Write Cycle
Reserved
VPD Operation
FUNCTION
VPD Data
TYPE
TYPE
TYPE
TYPE
TYPE
RO /
RW
RW
RW
RW
RO
RO
RO
RO
Page 65 of 145
DESCRIPTION
If Hot Swap is enabled, this counter is read-write able. This counter is read
only (RO) if Hot Swap is disabled
00h: 1ms
01h: 2ms
02h: 3ms
03h: 4ms
FFh: 256ms
Reset to 0
DESCRIPTION
Reset to 03h
DESCRIPTION
Next pointer (F0h, points to MSI capabilities)
Reset to F0h
DESCRIPTION
Reset to 0
Reset to 0
Reset to 0
0: Generate a read cycle from the EEPROM at the VPD address specified in
bits [7:2] of offset D8h. This bit remains at ‘0’ until EEPROM cycle is
finished, after which the bit is then set to ‘1’. Data for reads is available at
register ECh.
1: Generate a write cycle to the EEPROM at the VPD address specified in
bits [7:2] of offset D8h. This bit remains at ‘1’ until EEPROM cycle is
finished, after which it is then cleared to ‘0’.
Reset to 0
DESCRIPTION
VPD Data (EEPROM data [address + 0x40])
The least significant byte of this register corresponds to the byte of VPD at
the address specified by the VPD address register. The data read form or
written to this register uses the normal PCI byte transfer capabilities.
Reset to 0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110

Related parts for PI7C9X110