PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 26

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

6
6.1
6.2
7
PCI Express TLP (Transaction Layer Packet) Structure is comprised of format, type, traffic class, attributes, TLP
digest, TLP poison, and length of data payload.
There are four TLP formats defined in PI7C9X110 based on the states of FMT [1] and FMT [0] as shown on Table
6-1.
Table 6-1 TLP Format
Data payload of PI7C9X110 can range from 4 (1DW) to 256 (64DW) bytes. PI7C9X110 supports three TLP
routing mechanisms. They are comprised of Address, ID, and Implicit routings. Address routing is being used for
Memory and IO requests. ID based (bus, device, function numbers) routing is being used for configuration
requests. Implicit routing is being used for message routing. There are two message groups (baseline and advanced
switching). The baseline message group contains INTx interrupt signaling, power management, error signaling,
locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. The other is
advanced switching support message group. The advanced switching support message contains data packet and
signal packet messages. Advanced switching is beyond the scope of PI7C9X110 implementation.
The r [2:0] values of the "type" field will determine the destination of the message to be routed. All baseline
messages must use the default traffic class zero (TC0).
This section provides a summary of Virtual Isochronous Operation supported by PI7C9X110. Virtual Isochronous
support is disabled by default. Virtual Isochronous feature can be turned on with setting bit [26] of offset 40h to
one. Control bits are designated for selecting which traffic class (TC1-7) to be used for upstream (PCI Express-to-
PCI). PI7C9X110 accepts only TC0 packets of configuration, IO, and message packets for downstream (PCI
Express-to-PCI). If configuration, IO and message packets have traffic class other than TC0, PI7C9X110 will treat
them as malformed packets. PI7C9X110 maps all downstream memory packets from PCI Express to PCI
transactions regardless the virtual Isochronous operation is enabled or not.
PI7C9X110 supports Type-0 (non-transparent bridge mode) and Type-1 (transparent bridge mode) configuration
space headers and Capability ID of 01h (PCI power management) to 10h (PCI Express capability structure).
With pin REVRSB = 0, device-port type (bit [7:4]) of capability register will be set to 7h (PCI Express-to-PCI/PIC-
X bridge). When pin REVRSB = 1, device-port type (bit [7:4]) of capability register will be set to 8h (PCI/PCI-X-
to-PCI Express bridge).
PI7C9X110 supports PCI Express capabilities register structure with capability version set to 1h (bit [3:0] of offset
02h).
Pericom Semiconductor
PCI EXPRESS FUNCTIONAL OVERVIEW
TLP STRUCTURE
VIRTUAL ISOCHRONOUS OPERATION
CONFIGURATION REGISTERS
FMT [1]
0
0
1
1
FMT [0]
0
1
0
1
TLP Format
3 double word, without data
4 double word, without data
3 double word, with data
4 double word, with data
Page 26 of 145
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110