PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 28

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

Pericom Semiconductor
Primary Bus
Configuration Access
for both Transparent
and Non-Transparent
mode, or Secondary
Bus Configuration
Access for Transparent
Mode
27h – 26h
2Bh – 28h
2Dh – 2Ch
2Fh – 2Eh
31h – 30h
33h – 32h
34h
37h – 35h
3Bh – 38h
3Ch
3Dh
3Eh
3Fh
41h – 40h
43h – 42h
45h – 44h
47h – 46h
4Bh – 48h
4Ch
4Dh
4Eh
4Fh
53h – 50h
57h – 54h
5Bh – 58h
5Fh – 5Ch
63h – 60h
67h – 64h
69h – 68h
6Ah
6Bh
6Dh – 6Ch
6Fh – 6Eh
Secondary Bus
Configuration Access
for Non-Transparent
Mode Only
67h - 66h
2Bh – 28h
2Dh – 2Ch
2Fh – 2Eh
31h – 30h
33h – 32h
34h
37h – 35h
3Bh – 38h
7Ch
7Dh
7Eh
7Fh
41h – 40h
43h – 42h
05h – 04h
07h – 06h
4Bh – 48h
0Ch
0Dh
0Eh
0Fh
13h – 10h
17h – 14h
1Bh – 18h
1Fh – 1Ch
23h – 20h
27h – 24h
69h – 68h
6Ah
6Bh
6Dh – 6Ch
6Fh – 6Eh
Page 28 of 145
Transparent Mode
(type1)
Prefetchable Memory
Limit Register
Prefetchable Memory
Base Upper 32-bit
Register
Prefetchable Memory
Limit Upper 32-bit
Register
Prefetchable Memory
Limit Upper 32-bit
Register
I/O Base Upper 16-bit
Register
I/O Limit Upper 16-bit
Register
Capability Pointer
Reserved
Reserved
Interrupt Line
Interrupt Pin
Bridge Control
Bridge Control
PCI Data Buffering
Control
Chip Control 0
Reserved
Reserved
Arbiter Mode, Enable,
Priority
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCI Express Tx and Rx
Control
Reserved
Reserved
Reserved
Reserved
Non-Transparent
Mode (Type0)
Downstream Memory
3 Upper 32-bit BAR
Subsystem Vendor ID
Subsystem ID
Reserved
Reserved
Capability Pointer
Reserved
Reserved
Primary Interrupt Line
Primary Interrupt Pin
Primary Min_Gnt
Primary Max_Lat
PCI Data Buffering
Control
Chip Control 0
Secondary Command
Register
Secondary Status
Register
Arbiter Mode, Enable,
Priority
Secondary Cacheline
Size Register
Secondary Status
Register
Header Type
Reserved
Secondary CSR and
Memory 0 BAR
Secondary CSR I/O
BAR
Upstream I/O or
Memory 1 BAR
Upstream Memory 2
BAR
Upstream Memory 3
BAR
Upstream Memory 3
Upper 32-bit BAR
PCI Express Tx and Rx
Control
Memory Address
Forwarding Control
Reserved
Subsystem Vendor ID
Subsystem ID
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
EEPROM
(I2C)
Access
No
No
Yes2
Yes2
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
No
Yes
No
No
No
-
No
No
No
No
No
No
Yes
Yes
No
Yes
Yes
3
3
3
2
2
PI7C9X110
SM Bus
Access
Yes
Yes
Yes5
Yes5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
3
3
3
5
5