PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 136

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

14
14.1 INSTRUCTION REGISTER
14.2 BYPASS REGISTER
14.3 DEVICE ID REGISTER
at an average interval between 1180 to 1538 Symbol Times. PI7C9X110 does not keep PCI/PCI-X reset active
when VD33 power is off even though VAUX (3.3v) is supported. It is recommended to add a weak pull-down
resistor on its application board to ensure PCI/PCI-X reset is low when VD33 power is off (see section 7.3.2 of PCI
Bus Power management Specification Revision 1.1).
In reverse bridge mode, PI7C9X110 generates fundamental reset (PERST_L) and then 1024 TS1 order-sets with
reset bit set when PCI/PCI-X reset (RESET_L) is asserted to PI7C9X110. PI7C9X110 has scheduling skip order-
set for insertion at an interval between 1180 and 1538 Symbol Times.
PI7C9X110 transmits one Electrical Idle order-set and enters to Electrical Idle.
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support
boundary scan in PI7C9X110 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI,
TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers
including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the
Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to
ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the
PCI resource is operating PCI bus cycles.
PI7C9X110 implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined
instruction codes are shown in Table 14-1. Those bit combinations that are not listed are equivalent to the BYPASS
(11111) instruction:
Table 14-1 Instruction register codes
The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a bypass
instruction is in effect. This allows rapid movement of test data to and from other components on the board. This
path can be selected when no test operation is being performed on the PI7C9X110.
Pericom Semiconductor
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
Instruction
EXTEST
SAMPLE
HIGHZ
CLAMP
IDCODE
BYPASS
INT_SCAN
MEM_BIST
Operation Code (binary)
00000
00001
00101
00100
01100
11111
00010
01010
Register Selected
Boundary Scan
Boundary Scan
Bypass
Bypass
Device ID
Bypass
Internal Scan
Memory BIST
Page 136 of 145
Operation
Drives / receives off-chip test data
Samples inputs / pre-loads outputs
Tri-states output and I/O pins except TDO pin
Drives pins from boundary-scan register and selects Bypass register
for shifts
Accesses the Device ID register, to read manufacturer ID, part
number, and version number
Selected Bypass Register
Scan test
Memory BIST test
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110