PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 17

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

Pericom Semiconductor
NAME
IRDY_L
TRDY_L
DEVSEL_L
STOP_L
LOCK_L
IDSEL
PERR_L
SERR_L
REQ_L [7:0]
GNT_L [7:0]
CLKOUT [8:0]
RESET_L
INTA_L
INTB_L
INTC_L
INTD_L
FBCLKIN
CLKIN
PIN ASSIGNMENT
D10
A11
B11
A12
A13
N14
A14
B14
P2, P1, N3, N2, N1,
M3, M2, M1
N6, P6, P5, N5, M5,
L5, N4, M4
N12, P12, N11, L10,
M10, P10, L9, N9, P9
N7
P3
M6
P13
N13
C2
P7
TYPE
IOD
IOD
O
O
B
B
B
B
B
B
B
I
I
I
I
Page 17 of 145
DESCRIPTION
IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to
complete current data phase on the primary side. Once asserted in a data phase, it is
not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-
asserted state for one cycle.
TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to
complete current data phase on the primary side. Once asserted in a data phase, it is
not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-
asserted state for one cycle.
Device Select (Active LOW): Asserted by the target indicating that the device is
accepting the transaction. As a master, PI7C9X110 waits for the assertion of this
signal within 5 cycles of FRAME_L assertion; otherwise, terminate with master
abort. Before tri-stated, it is driven to a de-asserted state for one cycle.
STOP (Active LOW): Asserted by the target indicating that the target is requesting
the initiator to stop the current transaction. Before tri-stated, it is driven to a de-
asserted state for one cycle.
LOCK (Active LOW): Asserted by the initiator for multiple transactions to
complete. PI7C9X110B does not support any upstream LOCK transaction.
Initialization Device Select: Used as a chip select line for Type 0 configuration
access to bridge’s configuration space.
Parity Error (Active LOW): Asserted when a data parity error is detected for data
received on the PCI bus interface. Before being tri-stated, it is driven to a de-asserted
state for one cycle.
System Error (Active LOW): Can be driven LOW by any device to indicate a
system error condition. If SERR control is enabled, PI7C9X110B will drive this pin
on:
This signal is an open drain buffer that requires an external pull-up resistor for proper
operation.
Request (Active LOW): REQ_L’s are asserted by bus master devices to request for
transactions on the PCI bus. The master devices de-assert REQ_Ls for at least 2 PCI
clock cycles before asserting them again. If external arbiter is selected (CFN_L=1),
REQ_L [0] will be the bus grant input to PI7C9X110. Also, REQ_L [5:2] will
become the GPI [3:0].
Grant (Active LOW): PI7C9X110 asserts GNT_Ls to release PCI bus control to bus
master devices. During idle and all GNT_Ls are de-asserted and arbiter is parking to
PI7C9X110, PI7C9X110 will drive AD, CBE, and PAR to valid logic levels. If
external arbiter is selected (CFN_L=1), GNT_L [0] will be the bus request from
PI7C9X110 to external arbiter. Also, GNT_L [5:2] will become the GPO [3:0].
PCI Clock Outputs: PCI clock outputs are derived from the CLKIN and provide
clocking signals to external PCI Devices.
RESET_L (Active LOW): When RESET_L active, all PCI signals should be
asynchronously tri-stated.
Interrupt: Signals are asserted to request an interrupt. After asserted, it can be
cleared by the device driver. INTA_L, INTB_L, INTC_L, INTD_L signals are inputs
and asynchronous to the clock in the forward mode. In reverse mode, INTA_L,
INTB_L, INTC_L, and INTD_L are open drain buffers for sending interrupts to the
host interrupt controller.
Feedback Clock Input: It connects to one of the CLKOUT [8:0] Output Signals and
provides internal clocking to PI7C9X110 PCI bus interface.
PCI Clock Input: PCI Clock Input Signal connects to an external clock source.
PI7C9X110 supports various PCI Frequency from 10MHz to 66MHz. The PCI Clock
Outputs CLKOUT [8:0] pins are derived from CLKIN Input.
Address parity error
Posted write data parity error on target bus
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
Errors reported from PCI Express port (advanced error reporting) in transparent
mode.
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110