PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 140

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PI7C9X110

Manufacturer Part Number
PI7C9X110
Description
Pcie-to-pci Reversible Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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0
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PI7C9X110 supports D0, D3-hot, D3-cold Power States. D1 and D2 states are not supported. The PCI Express
Physical Link Layer of the PI7C9X110 device supports the PCI Express Link Power Management with L0, L0s, L1,
L2/L3 ready and L3 Power States. For the PCI Port of PI7C9X110, it supports the standard PCI Power
Management States with B0, B1, B2 and B3.
During D3-hot state, the main power supplies of VDDP, VDDC, and VD33 can be turned off to save power while
keeping the VDDAUX, VDDCAUX, and VAUX with the auxiliary power supplies to maintain all necessary
information to be restored to the full power D0 state. PI7C9X110 has been designed to have sticky registers that are
powered by auxiliary power supplies. PME_L pin allows PCI devices to request power management state changes.
Along with the operating system and application software, PCI devices can achieve optimum power saving by using
PME_L in forward bridge mode. PI7C9X110 converts PME_L signal information to power management messages
to the upstream switches or root complex. In reverse bridge mode, PI7C9X110 converts the power management
event messages from PCIe devices to the PME_L signal and continues to request power management state change
to the host bridge.
PI7C9X110 also supports ASPM (Active State Power Management) to facilitate the link power saving.
PI7C9X110 supports Beacon generation but does not support WAKE# signal.
Pericom Semiconductor
POWER MANAGEMENT
Register Number
Boundary Scan
149
150
151
152
153
Pin Name
REVRSB
MSK_IN
INTD_L
IDSEL
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Page 140 of 145
Ball Location
M12
N13
N14
P14
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CONTROL
INPUT
INPUT
INPUT
BIDIR
Type
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
Tri-state Control Cell
151
PI7C9X110
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