PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 105

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.72 DONWSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET A8h
Pericom Semiconductor
BIT
8
9
10
11
12
13
14
15
31:16
BIT
5:0
31:6
FUNCTION
S_CLKOUT4 Enable
S_CLKOUT5 Enable
S_CLKOUT6 Enable
S_CLKOUT7 Enable
S_CLKOUT8 Enable
Secondary Clock Stop Status
Secondary Clkrun Protocol
Enable
Clkrun Mode
Reserved
FUNCTION
Reserved
Downstream I/O or Memory
1 Translated Base
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
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DESCRIPTION
S_CLKOUT (Device 1) Enable for forward bridge mode only
0: enable S_CLKOUT4
1: disable S_CLKOUT4 and driven LOW
Reset to 0
S_CLKOUT (Device 2) Enable for forward bridge mode only
0: enable S_CLKOUT5
1: disable S_CLKOUT5 and driven LOW
Reset to 0
S_CLKOUT (Device 3) Enable for forward bridge mode only
0: enable S_CLKOUT6
1: disable S_CLKOUT6 and driven LOW
Reset to 0
S_CLKOUT (Device 4) Enable for forward bridge mode only
0: enable S_CLKOUT7
1: disable S_CLKOUT7 and driven LOW
Reset to 0
S_CLKOUT (the bridge) Enable for forward bridge mode only
0: enable S_CLKOUT8
1: disable S_CLKOUT8 and driven LOW
Reset to 0
Secondary clock stop status
0: secondary clock not stopped
1: secondary clock stopped
Reset to 0
0: disable protocol
1: enable protocol
Reset to 0
0: Stop the secondary clock only when bridge is at D3hot state
1: Stop the secondary clock whenever the secondary bus is idle and there are
no requests from the primary bus
Reset to 0
Reset to 0000h
DESCRIPTION
Reset to 000000
Define the translated base address for downstream I/O or memory
transactions whose initiator addresses fall into Downstream I/O or Memory 1
address range. The number of bits that are used for translated base is
determined by its setup register (offset ACh)
Reset to 00000h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110