PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 98

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.53 SECONDARY MAXIMUM LATENCY TIMER REGISTER – OFFSET 7Ch
7.5.54 PCI-X CAPABILITY ID REGISTER – OFFSET 80h
7.5.55 NEXT CAPABILITY POINTER REGISTER – OFFSET 80h
7.5.56 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h
Pericom Semiconductor
BIT
31:24
BIT
7:0
BIT
15:8
BIT
16
17
18
19
20
21
FUNCTION
Secondary Maximum
Latency Timer
FUNCTION
PCI-X Capability ID
FUNCTION
Next Capability Pointer
FUNCTION
64-bit Device on Secondary
Bus Interface
133MHz Capable
Split Completion Discarded
Unexpected Split
Completion
Split Completion Overrun
Split Request Delayed
TYPE
TYPE
TYPE
TYPE
RWC
RWC
RWC
RWC
RO /
RO
RO
RO
RO
RO
Page 98 of 145
DESCRIPTION
This register is valid only in forward bridge mode. It specifies how often that
PI7C9X110 needs to gain access to the primary bus in units of ¼
microseconds.
Reset to 0
DESCRIPTION
PCI-X Capability ID
Reset to 07h
DESCRIPTION
Point to power management
Reset to 90h
DESCRIPTION
64-bit not supported
Reset to 0
When this bit is 1, PI7C9X110 is 133MHz capable on its secondary bus
interface
Reset to 1 in forward bridge mode or 0 in reverse bridge mode
This bit is a read-only and set to 0 in reverse bridge mode or is read-write in
forward bridge mode
When this is set to 1, a split completion has been discarded by PI7C9X110 at
secondary bus because the requester did not accept the split completion
transaction
Reset to 0
This bit is set to 0 in forward bridge mode or is read-write in reverse bridge
mode
When this is set to 1, an unexpected split completion has been received with
the requester ID equaled to the secondary bus number, device number, and
function number at the PI7X9X110 secondary bus interface
Reset to 0
When this bit is set to 1, a split completion has been terminated by
PI7C9X110 with either a retry or disconnect at the next ADB due to the
buffer full condition
Reset to 0
When this bit is set to 1, a split request is delayed because PI7C9X110 is not
able to forward the split request transaction to its secondary bus due to
insufficient room within the limit specified in the split transaction
commitment limit field of the downstream split transaction control register
Reset to 0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110