PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 18

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.4
2.5
2.6
Pericom Semiconductor
MODE SELECT AND STRAPPING SIGNALS
NAME
TM2
TM1
TM0
MSK_IN
REVRSB
CFN_L
JTAG BOUNDARY SCAN SIGNALS
NAME
TCK
TMS
TDO
TDI
TRST_L
MISCELLANEOUS SIGNALS
NAME
GPIO [3:0]
SMBCLK /
SCL
SMBDATA /
SDA
PME_L
CLKRUN_L
PIN ASSIGNMENT
K3
C1
D1
P14
M12
M7
PIN ASSIGNMENT
L14
L13
M13
M14
K11
PIN ASSIGNMENT
L7, P8, M8, L8
A2
A1
A3
D3
TYPE
TYPE
TYPE
B/IOD
ID
IU
IU
IU
IU
O
B
B
B
B
I
I
I
I
I
Page 18 of 145
DESCRIPTION
Mode Select 2: TM2 is a strapping pin. When TM2 is strapped low for normal
operations and strapped high for testing functions. See table 3-1 for mode selection
and 3-2 for strapping control for details.
Mode Select 1: Mode Selection Pin to select EEPROM or SM Bus. TM1=0 for
EEPROM (I2C) support and TM1=1 for SM Bus support. TM1 is also a strapping
pin. See table 3-1 mode selection and 3-2 for strapping control.
Mode Select 0: Mode Selection Pin to select transparent or non-transparent mode.
TM0=0 for transparent bridge function mode and TM0=1 for non-transparent bridge
function mode. TM0 is also a strapping pin. See table 3-1 for mode selection and 3-2
for strapping control.
Mask Input for CLKOUT: MSK_IN is used by PI7C9X110 to enable or disable the
clock outputs. MSK_IN is also a strapping pin. When it is strapped to high, hot-plug
is enabled. See table 3-2 for strapping control.
Forward or Reverse Bridging Pin: REVRSB pin controls the Forward
(REVRSB=0) or Reverse (REVRSB=1) Bridge Mode of PI7C9X110. This pin is also
a strapping pin. See table 3-1 for mode selection.
Bus Central Function Control Pin (Active Low): To enable the internal arbiter,
CFN_L pin should be tied low. When it’s tied high, an external arbiter is required to
arbitrate the bus. In external arbiter mode, REQ_L [0] is re-configured to be the
secondary bus grant input, and GNT_L [0] is reconfigured to be the secondary bus
request output. Also, REQ_L [5:2] and GNT_L [5:2] become GPI [3:0] and GPO
[3:0] respectively if external arbiter is selected. CFN_L has a weak internal pull-down
resistor. See table 3-1 for mode selection.
DESCRIPTION
Test Clock: TCK is the test clock to synchronize the state information and data on
the PCI bus side of PI7C9X110 during boundary scan operation.
Test Mode Select: TMS controls the state of the Test Access Port (TAP) controller.
Test Data Output: TDO is the test data output and connects to the end of the JTAG
scan chain.
Test Data Input: TDI is the test data input and connects to the beginning of the
JTAG scan chain. It allows the test instructions and data to be serially shifted into the
PCI side of PI7C9X110.
Test Reset (Active LOW): TRST_L is the test reset to initialize the Test Access Port
(TAP) controller.
DESCRIPTION
General Purpose I/O Data Pins: The 4 general-purpose signals are programmable as
either input-only or bi-directional signals by writing the GPIO output enable control
register in the configuration space. See Chapter 8 for more information.
SMBUS / EEPROM Clock Pin: When EEPROM (I2C) interface is selected
(TM1=0), this pin is an output of SCL clock and connected to EEPROM clock input.
When SMBUS interface is selected (TM1=1), this pin is an input for the clock of
SMBUS.
SMBUS / EEPROM Data Pin: Data Interface Pin to EERPOM or SMBUS. When
EEPROM (I2C) interface is selected (TM1=0), this pin is a bi-directional signal.
When SMBUS interface is selected (TM1=1), this pin is an open drain signal.
Power Management Event Pin: Power Management Event Signal is asserted to
request a change in the device or link power state.
Clock Run Pin (Active LOW): The Clock Run signal, for mobile environment, is
asserted and de-asserted to indicate the status of the PCI Clock.
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110