PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 53

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.4.49 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h
7.4.50 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch
Pericom Semiconductor
BIT
18
19
20
21
31:22
BIT
15:0
31:16
BIT
15:0
FUNCTION
Split Completion Discarded
Unexpected Split
Completion
Split Completion Overrun
Split Request Delayed
Reserved
FUNCTION
Upstream Split Transaction
Capability
Upstream Split Transaction
Commitment Limit
FUNCTION
Downstream Split
Transaction Capability
TYPE
TYPE
TYPE
RWC
RWC
RWC
RWC
RO /
RW
RO
RO
RO
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DESCRIPTION
This bit is a read-only and set to 0 in reverse bridge mode or is read-write in
forward bridge mode
When this is set to 1, a split completion has been discarded by PI7C9X110 at
primary bus because the requester did not accept the split completion
transaction
Reset to 0
This bit is set to 0 in forward bridge mode or is read-write in reverse bridge
mode
When this is set to 1, an unexpected split completion has been received with
the requester ID equaled to the primary bus number, device number, and
function number at the PI7X9X110 primary bus interface
Reset to 0
When this bit is set to 1, a split completion has been terminated by
PI7C9X110 with either a retry or disconnect at the next ADB due to the
buffer full condition
Reset to 0
When this bit is set to 1, a split request is delayed because PI7C9X110 is not
able to forward the split request transaction to its primary bus due to
insufficient room within the limit specified in the split transaction
commitment limit field of the downstream split transaction control register
Reset to 0
0000000000
DESCRIPTION
Upstream Split Transaction Capability specifies the size of the buffer (in the
unit of ADQs) to store split completions for memory read. It applies to the
requesters on the secondary bus in addressing the completers on the primary
bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes
storage
Reset to 0010h
Upstream Split Transaction Commitment Limit indicates the cumulative
sequence size of the commitment limit in units of ADQs. This field can be
programmed to any value or equal to the content of the split capability field.
For example, if the limit is set to FFFFh, PI7C9X110 is allowed to forward
all split requests of any size regardless of the amount of buffer space
available. The split transaction commitment limit is set to 0010h that is the
same value as the split transaction capability.
Reset to 0010h
DESCRIPTION
Downstream Split Transaction Capability specifies the size of the buffer (in
the unit of ADQs) to store split completions for memory read. It applies to
the requesters on the primary bus in addressing the completers on the
secondary bus. The 0010h value shows that the buffer has 16 ADQs or 2K
bytes storage
Reset to 0010h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110