PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 55

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.4.54 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h
7.4.55 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h
7.4.56 RESERVED REGISTERS – OFFSET 98h – 9Ch
7.4.57 CAPABILITY ID REGISTER – OFFSET A0h
7.4.58 NEXT POINTER REGISTER – OFFSET A0h
Pericom Semiconductor
BIT
1:0
7:2
8
12:9
14:13
15
BIT
21:16
22
23
31:24
BIT
7:0
BIT
15:8
FUNCTION
Power State
Reserved
PME Enable
Data Select
Data Scale
PME Status
FUNCTION
Reserved
B2/B3 Support
PCI Bus Power/Clock
Control Enable
Data Register
FUNCTION
Capability ID
FUNCTION
Next Pointer
RWCS
TYPE
TYPE
TYPE
TYPE
RWS
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Power State is used to determine the current power state of PI7C9X110. If a
non-implemented state is written to this register, PI7C9X110 will ignore the
write data. When present state is D3 and changing to D0 state by
programming this register, the power state change causes a device reset
without activating the RESET_L of PCI/PCI-X bus interface
00: D0 state
01: D1 state not implemented
10: D2 state not implemented
11: D3 state
Reset to 00
Reset to 000000
0: PME_L assertion is disabled
1: PME_L assertion is enabled
Reset to 0
Data register is not implemented
Reset to 0000
Data register is not implemented
Reset to 00
PME_L is supported
Reset to 0
DESCRIPTION
Reset to 000000
0: B2 / B3 not support for D3hot
Reset to 0
0: PCI Bus Power/Clock Disabled
Reset to 0
Data register is not implemented
Reset to 00h
DESCRIPTION
Capability ID for Slot Identification. SI is off by default but can be turned on
through EEPROM interface
Reset to 04h
DESCRIPTION
Next pointer – points to PCI Express capabilities register
Reset to B0h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110