PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 113

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.89 CAPABILITY ID REGISTER – OFFSET D8h
7.5.90 NEXT POINTER REGISTER – OFFSET D8h
7.5.91 VPD REGISTER – OFFSET D8h
7.5.92 VPD DATA REGISTER – OFFSET DCh
7.5.93 UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET E0h
Pericom Semiconductor
BIT
15
22:16
31:23
BIT
7:0
BIT
15:8
BIT
17:16
23:18
30:24
31
BIT
31:0
BIT
11:0
31:12
FUNCTION
Reserved
L1 Exit to L0 Latency
Reserved
FUNCTION
Capability ID for VPD
Register
FUNCTION
Next Pointer
FUNCTION
Reserved
VPD Address for
Read/Write Cycle
Reserved
VPD Operation
FUNCTION
VPD Data
FUNCTION
Reserved
Downstream Memory 0
Translated Base
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Reset to 0
Reset to 19h
Reset to 0
DESCRIPTION
Reset to 03h
DESCRIPTION
Next pointer (F0h, points to MSI capabilities)
Reset to F0h
DESCRIPTION
Reset to 0
Reset to 0
Reset to 0
0: Generate a read cycle from the EEPROM at the VPD address specified in
bits [7:2] of offset D8h. This bit remains at ‘0’ until EEPROM cycle is
finished, after which the bit is then set to ‘1’. Data for reads is available at
register ECh.
1: Generate a write cycle to the EEPROM at the VPD address specified in
bits [7:2] of offset D8h. This bit remains at ‘1’ until EEPROM cycle is
finished, after which it is then cleared to ‘0’.
Reset to 0
DESCRIPTION
VPD Data (EEPROM data [address + 0x40])
The least significant byte of this register corresponds to the byte of VPD at
the address specified by the VPD address register. The data read form or
written to this register uses the normal PCI byte transfer capabilities.
Reset to 0
DESCRIPTION
Reset to 000h
Define the translated base address for upstream memory transactions whose
initiator addresses fall into Upstream Memory 0 (above lower 4K boundary)
address range. The number of bits that are used for translated base is
determined by its setup register (offset E4h)
Reset to 00000h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110