PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 82

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.24 PRIMARY MAXIMUM LATENCY TIME REGISTER – OFFSET 3Ch
7.5.25 PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h
Pericom Semiconductor
BIT
31:24
BIT
0
1
2
3
5:4
7:6
FUNCTION
Primary Maximum Latency
Timer
FUNCTION
Secondary Internal Arbiter’s
PARK Function
Memory Read Prefetching
Dynamic Control Disable
Completion Data Prediction
Control
Reserved
PCI Read Multiple Prefetch
Mode
PCI Read Line Prefetch
Mode
TYPE
TYPE
RW
RW
RW
RW
RW
RO
RO
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DESCRIPTION
This register is valid only in reverse bridge mode. It specifies how often that
PI7C9X110 needs to gain access to the primary bus in units of ¼
microseconds.
Reset to 0
DESCRIPTION
0: Park to the last master
1: Park to PI7C9X110 secondary port
Reset to 0
0: Enable memory read prefetching dynamic control for PCI to PCIe read
1: Disable memory read prefetching dynamic control for PCI to PCIe read
Reset to 0
0: Enable completion data prediction for PCI to PCIe read.
1: Disable completion data prediction
Reset to 0
Reset to 0
These two bits are ignored in PCI-X mode.
00: One cache line prefetch if memory read multiple address is in
prefetchable range at the PCI interface
01: Full prefetch if address is in prefetchable range at PCI interface, and the
PI7C9X110 will keep remaining data after it disconnects the external master
during burst read with read multiple command until the discard timer expires
10: Full prefetch if address is in prefetchable range at PCI interface
11: Full prefetch if address is in prefetchable range at PCI interface and the
PI7C9X110 will keep remaining data after the read multiple is terminated
either by an external master or by the PI7C9X110, until the discard time
expires
Reset to 10
These two bits are ignored in PCI-X mode.
00: Once cache line prefetch if memory read address is in prefetchable range
at PCI interface
01: Full prefetch if address is in prefetchable range at PCI interface and the
PI7C9X110 will keep remaining data after it is disconnected by an external
master during burst read with read line command, until discard timer expires
10: Full prefetch if memory read line address is in prefetchable range at PCI
interface
11: Full prefetch if address is in prefetchable range at PCI interface and the
PI7C9X110 will keep remaining data after the read line is terminated either
by an external master or by the PI7C9X110, until the discard timer expires
Reset to 00
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110