PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 36

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.4.8
7.4.9
7.4.10 RESERVED REGISTERS – OFFSET 10h TO 17h
7.4.11 PRIMARY BUS NUMBER REGISTER – OFFSET 18h
7.4.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h
7.4.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
7.4.14 SECONDARY LATENCY TIME REGISTER – OFFSET 18h
Pericom Semiconductor
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch
BIT
5
7:6
BIT
15:8
BIT
22:16
23
31:24
BIT
7:0
BIT
15:8
BIT
23:16
BIT
31:24
FUNCTION
Cache Line Size
Reserved
FUNCTION
Primary Latency Timer
FUNCTION
PCI-to-PCI bridge
configuration
(transparent mode)
Other bridge configuration
(non-transparent mode)
Single Function Device
Reserved
FUNCTION
Primary Bus Number
FUNCTION
Secondary Bus Number
FUNCTION
Subordinate Bus Number
FUNCTION
Secondary Latency Timer
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
RW /
RO /
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Reset to 0
1: Cache line size = 32 double words
Reset to 0
Bit [7:6] not supported
Reset to 00
DESCRIPTION
8 bits of primary latency timer in PCI/PCI-X
FORWARD BRIDGE – RO with reset to 00h
REVERSE BRIDGE – RW with reset to 00h in PCI mode or 40h in PCI-X
mode
DESCRIPTION
PCI-to-PCI bridge configuration (10 – 3Fh)
Reset to 0000001 (transparent mode)
Type-0 header format configuration (10-3Fh)
Reset to 0000000 (non-transparent mode)
0: Indicates single function device
Reset to 0
Reset to 00h
DESCRIPTION
Reset to 00h
DESCRIPTION
Reset to 00h
DESCRIPTION
Reset to 00h
DESCRIPTION
Secondary latency timer in PCI / PCI-X mode
FORWARD BRIDGE –
RW with reset to 00h in PCI mode or 40h in PCI-X mode
REVERSE BRIDGE –
RO with reset to 00h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110