PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 78

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.11 PRIMARY CSR I/O BASE ADDRESS REGISTER – OFFSET 14h
7.5.12 DOWNSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 18h
Pericom Semiconductor
BIT
2:1
3
11:4
31:12
BIT
0
7:1
31:8
BIT
0
2:1
3
11:4
31:12
FUNCTION
Address Type
Prefetchable control
Reserved
Base Address
FUNCTION
Space Indicator
Reserved
Base Address
FUNCTION
Space Indicator
Address Type
Prefetchable control
Reserved
Base Address
RW/RO
RO/RW
RW/RO
TYPE
TYPE
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from
Downstream Memory 0 Setup Register (Offset 9Ch), which can be initialized
by EEPROM (I2C) or SM Bus or Local Processor. The range of this register
is from 4KB to 2GB. The lower 4KB if this address reange map to the
PI7C9X110 CSRs into memory space. The remaining space is this range
above 4KB, if any, specifies a range for forwarding downstream memory
transactions. PI7X9X110 uses downstream Memory 0 Translated Base
Register (Offset 98h) to formulate direct address translation. If a bit in the
setup register is set to one, then the correspondent bit of this register will be
changed to RW.
Reset to 00000h
DESCRIPTION
0: Memory space
1: IO space
Reset to 1
Reset to 0
This Base Address Register maps to PI7C9X110 primary IO space. The
maximum size is 256 bytes.
Reset to 00000000h
DESCRIPTION
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from
Downstream IO or Memory 1 Setup Register (Offset ACh), which can be
initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero
to bit [31] of the setup register to disable this register. The range of this
register is from 4KB to 2GB for memory space or from 64B to 256B for IO
space. PI7X9X110 uses downstream IO or Memory 1 Translated Base
Register (Offset A8h) to formulate direct address translation. If a bit in the
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110