PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 90

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.36 SECONDARY CSR I/O BASE ADDRESS REGISTER – OFFSET 54h
7.5.37 UPSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 58h
Pericom Semiconductor
BIT
2:1
3
11:4
31:12
BIT
0
7:1
31:8
BIT
0
2:1
3
5:4
FUNCTION
Address Type
Prefetchable control
Reserved
Base Address
FUNCTION
Space Indicator
Reserved
Base Address
FUNCTION
Space Indicator
Address Type
Prefetchable control
Reserved
RW/RO
RO/RW
TYPE
TYPE
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 90 of 145
DESCRIPTION
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from Upstream
Memory 0 Setup Register (Offset E4h), which can be initialized by
EEPROM (I2C) or SM Bus or Local Processor. The range of this register is
from 4KB to 2GB. The lower 4KB if this address reange map to the
PI7C9X110 CSRs into memory space. The remaining space is this range
above 4KB, if any, specifies a range for forwarding upstream memory
transactions. PI7X9X110 uses upstream Memory 0 Translated Base Register
(Offset E0h) to formulate direct address translation. If a bit in the setup
register is set to one, then the correspondent bit of this register will be
changed to RW.
Reset to 00000h
DESCRIPTION
0: Memory space
1: IO space
Reset to 1
Reset to 0
This Base Address Register maps to PI7C9X110 secondary IO space. The
maximum size is 256 bytes.
Reset to 00000000h
DESCRIPTION
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110