PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 24

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

5
5.1
5.2
In transparent bridge mode, base class code of PI7C9X110 is set to be 06h (bridge device). The sub-class code is
set to be 04h (PCI-to-PCI bridge). Programming interface is 00h. Hence, PI7C9X110 is not a subtractive decoding
bridge.
PI7C9X110 has type-1 configuration header if TM0 is set to 0 (transparent bridge mode). These configuration
registers are the same as traditional transparent PCI-to-PCI Bridge. In fact, it is backward compatible to the
software that supporting traditional transparent PCI-to-PCI bridges. Configuration registers can be accessed from
several different ways. For PCI Express access, PCI Express configuration transaction is in forward bridge mode.
For PCI access, PCI configuration cycle is mainly in reverse bridge mode. However, PI7C9X110 allows PCI
configuration access in forward mode as secondary bus configuration access. For I2C access, I2C bus protocol is
used with EEPROM selected (TM1=0). For SM bus access, SM bus protocol is used with SM bus selected
(TM1=1).
In non-transparent bridge mode, base class code of PI7C9X110 is set to be 06h (bridge device). The sub-class code
is set to be 80h (other bridge). Programming interface is 00h. Hence, PI7C9X110 is not a subtractive decoding
bridge.
PI7C9X110 has type-0 configuration header if TM0 is set to 1 (non-transparent mode). The configuration registers
are similar to a traditional PCI device. However, there is one set of configuration registers for the primary interface
and another set of configuration registers for the secondary interface. In addition, CSRs (Control and Status
Registers) are implemented to support the memory or IO transfers between the primary and secondary buses. The
CSRs are accessed through memory transaction access within the lowest memory range of 4K Space (bit [64:12] are
zeros). The non-transparent configuration registers can be accessed through several different ways (PCI Express,
PCI, I2C, and SM bus). For PCI Express and PCI access, the type-0 configuration transactions need to be used. For
I2C access, I2C bus protocol needs to be used through I2C bus interface. For SM bus access, SM bus protocol
needs to be used through SM bus interface. The hardware pins (A2 and A1) are shared for I2C and SM bus
interface. If TM1=0, pin A2 and A1 will be SCL and SDA for I2C interface respectively. If TM1=1, pin A2 and
A1 will be SMBCLK and SMBDATA for SM Bus interface respectively.
In non-transparent bridge mode, PI7C9X110 supports four or three memory BARs (Base Address Registers) and
one or two IO BARs (Base Address Registers) depending on selection on the primary bus. Also, PI7C9X110
supports four or three memory BARs (Base Address Registers) and one or two IO BARs (Base Address Registers)
depending on selection on the secondary bus.
Offset 10h is defined to be primary CSR and downstream memory 0 BAR. Offset 14h is defined to be primary CSR
and downstream IO BAR. Offset 18h is defined to be downstream memory 1 or IO BAR (selectable by CSR setup
register). Offset 1Ch is defined to be downstream memory 2 BAR. Offset 20h and 24h are defined to be
downstream memory 3 lower BAR and memory 3 upper BAR respectively to support 64-bit decoding.
The direct offset translation of address from primary to secondary bus will be done by substituting the original Base
Address at primary with the downstream Translation Base Address Register values and keeping the lower address
bits the same to form a new address for forward the transaction to secondary bus.
For downstream memory 2, it uses direct address translation. There is no lookup table for downstream memory
address translation.
Pericom Semiconductor
TRANSPARENT AND NON-TRANSPARENT BRIDGING
TRANSPARENT MODE
NON-TRANSPARENT MODE
Page 24 of 145
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110