PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 25

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

Offset 50h is defined to be secondary CSR and upstream memory 0 BAR. Offset 54h is defined to be secondary
CSR and upstream IO BAR. Offset 58h is defined to be upstream memory 1 or IO BAR (selectable by CSR setup
register offset E4h). Offset 1Ch is defined to be upstream memory 2 BAR. Offset 60h and 64h are defined to be
upstream memory 3 lower BAR and memory 3 upper BAR respectively to support 64-bit decoding.
The direct offset translation of address from secondary to primary bus will be done by substituting the original Base
Address at secondary with the upstream Translation Base Address Register values and keeping the lower address
bits the same to form a new address for forward the transaction to primary bus.
For upstream memory 2, it uses lookup table address translation method which using the original base address as
index to select a new address on the upstream memory 2 lookup table based on the page and window size defined.
Table 5-1 Non-transparent Registers
Pericom Semiconductor
Non-transparent Registers
Primary CSR and Memory 0 BAR
Downstream Memory 0 Translated Base
Downstream Memory 0 Setup
Downstream I/O or Memory 1 BAR
Downstream I/O or Memory 1 Translated Base
Downstream I/O or Memory 1 Setup
Downstream Memory 2 BAR
Downstream Memory 2 Translated Base
Downstream Memory 2 Setup
Downstream Memory 3 BAR
Downstream Memory 3 Upper 32-bit BAR
Downstream Memory 3 Translated Base
Downstream Memory 3 Setup
Downstream Memory 3 Upper 32-bit Setup
Secondary CSR Memory 0 BAR
Upstream Memory 0 Translated Base
Upstream Memory 0 Setup
Secondary CSR I/O BAR
Upstream I/O or Memory 1 BAR
Upstream I/O or Memory 1 Translated Base
Upstream I/O or Memory 1 Setup
Upstream Memory 2 BAR
Upstream Memory 2 Lookup Table Offset
Upstream Memory 2 Lookup Table Data
Upstream Memory 2 Lookup Table (64 32-bit entries)
Upstream Memory 3 BAR
Upstream Memory 3 Upper 32-bit BAR
Upstream Memory 3 Setup
Upstream Memory 3 Upper 32-bit Setup
Page 25 of 145
Typical access
Configuration access offset 10h
Configuration access offset A8h
Configuration access offset 27h
Lower 4K I/O or Memory access offset 018h
Configuration access offset 50h
Lower 4K I/O or Memory access offset 050h
Lower 4K I/O or Memory access offset 100h to 1FFh
Configuration access offset 67h
Lower 4K I/O or Memory access offset 34h
Lower 4K I/O or Memory access offset 38h
Configuration access offset 98h
Configuration access offset 9Ch
Configuration access offset 18h
Configuration access offset ACh
Configuration access offset 1Fh
Lower 4K I/O or Memory access offset 008h
Lower 4K I/O or Memory access offset 00Ch
Configuration access offset 23h
Lower 4K I/O or Memory access offset 010h
Lower 4K I/O or Memory access offset 014h
Configuration access offset E0h
Configuration access offset E4h
Configuration access offset 54h
Configuration access offset 58h
Configuration access offset E8h
Configuration access offset ECh
Configuration access offset 5Fh
Lower 4K I/O or Memory access offset 054h
Configuration access offset 63h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110