PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 127

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.6.13 UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER – OFFSET 058h
7.6.14 UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER – OFFSET 05Ch
Pericom Semiconductor
BIT
24:8
31:25
BIT
31:0
BIT
31:0
FUNCTION
Translated base or Reserved
Translated Base
FUNCTION
Upstream Page Boundary
IRQ 0
FUNCTION
Upstream Page Boundary
IRQ 1
RW/RO
TYPE
TYPE
TYPE
RWC
RWC
RW
Page 127 of 145
DESCRIPTION
Data written or read from the Lookup Table at the offset specified in the
Lookup Table Offset Register. When writing to this register, the data value
is written to the specified Lookup Table entry. When reading from this
register, the data reflects the data value from the specified Lookup Table
entry. The bit [24:8] is Translated Base Register bit when the lookup table
size is set to 256B range. The bit [24:8] is reserved when the lookup table
size is set to 32MB range (see PCI configuration offset 68h for non-
transparent mode).
Reset to 0
Data written or read from the Lookup Table at the offset specified in the
Lookup Table Offset Register. When writing to this register, the data value
is written to a specific Lookup Table entry (CSR offset 100h – 1FFh). When
reading from this register, the data reflects the data value from the specific
Lookup Table entry.
Reset to 0
DESCRIPTION
Each interrupt request bit is correspondent to a page entry in the lower half of
the Upstream Memory 2 range. Bit [0] is for the first page, and bit [31] is for
the 32
transfers data to or from the imitator that addresses the last Double Word in a
page. PI7C9X110 initiates an interrupt request on secondary interface when
the interrupt request bit is set and the corresponding Upstream Page
Boundary IRQ 0 Mask bit is reset. When forward bridge, PI7C9X110 asserts
INTA_L or generates MSI on secondary bus (PCI interface). When reverse
bridge, PI7C9X110 sends INTA_L assertion message or generates MSI on
secondary interface (PCI Express).
When writing a “1” to this register, it clears the corresponding interrupt
request bit.
Reset to 0
DESCRIPTION
Each interrupt request bit is correspondent to a page entry in the lower half of
the Upstream Memory 2 range. Bit [0] is for the 33
the 64
transfers data to or from the initiator that addresses the last Double Word in a
page. PI7C9X110 initiates an interrupt request on secondary interface when
the interrupt request bit is set and the corresponding Upstream Page
Boundary IRQ 1 Mask bit is reset. When forward bridge, PI7C9X110 asserts
INTA_L or generates MSI on secondary bus (PCI interface). When reverse
bridge, PI7C9X110 sends INTA_L assertion message or generates MSI on
secondary interface (PCI Express).
When wrting a “1” to this register, it clears the corresponding interrupt
request bit.
Reset to 0
nd
th
page. PI7C9X110 sets the appropriate bit when it successfully
page. PI7C9X110 sets the appropriate bit when it successfully
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
rd
page, and bit [31] is for
PI7C9X110