PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 85

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.28 SECONDARY STATUS REGISTER – OFFSET 44h
Pericom Semiconductor
BIT
2
3
4
5
6
7
8
9
10
15:11
BIT
18:16
19
20
FUNCTION
Bus Master Enable
Special Cycle Enable
Memory Write and
Invalidate Enable
VGA Palette Snoop Enable
Parity Error Response
Enable
Wait Cycle Control
Secondary SERR_L Enable
Bit
Fast Back-to-Back Enable
Secondary Interrupt Disable
Reserved
FUNCTION
Reserved
Secondary Interrupt Status
Capability List Capable
TYPE
TYPE
RO /
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
0: Do not initiate memory or I/O transactions on the secondary interface and
disable response to memory and I/O transactions on the secondary interface
1: Enable the PI7C9X110 to operate as a master on the secondary interfaces
for memory and I/O transactions forwarded from the secondary interface. If
the secondary of the reverse bridge is PCI-X mode, the PI7C9X110 is
allowed to initiate a split completion transaction regardless of the status bit.
Reset to 0
0: Bridge does not respond as a target to Special Cycle transactions, so this
bit is defined as Read-Only and must return 0 when read
Reset to 0
0: PI7C9X110 does not originate a Memory Write and Invalidate
transaction. Implements this bit as Read-Only and returns 0 when read
(unless forwarding a transaction for another master). This bit will be ignored
in PCI-X mode.
Reset to 0
0: Ignore VGA palette snoop access on the secondary
Reset to 0
0: May ignore any parity error that is detected and take its normal action
1: This bit if set, enables the setting of Master Data Parity Error bit in the
Status Register when poisoned TLP received or parity error is detected and
takes its normal action
Reset to 0
Wait cycle control not supported
Reset to 0
0: Disable
1: Enable PI7C9X110 in forward bridge mode to report non-fatal or fatal
error message to the Root Complex. Also, in reverse bridge mode to assert
SERR_L on the secondary interface
Reset to 0
Fast back-to-back enable not supported
Reset to 0
0: INTx interrupt messages can be generated
1: Prevent INTx messages to be generated and any asserted INTx interrupts
will be released.
Reset to 0
Reset to 00000
DESCRIPTION
Reset to 000
0: No INTx interrupt message request pending in PI7C9X110 secondary
1: INTx interrupt message request pending in PI7C9X110 secondary
Reset to 0
1: PI7C9X110 supports the capability list (offset 34h in the pointer to the
data structure)
Reset to 1
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110