PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 52

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.4.48 PCI-X BRIDGE STATUS REGISTER – OFFSET 84h
Pericom Semiconductor
BIT
20
21
24:22
31:25
BIT
2:0
7:3
15:8
16
17
FUNCTION
Split Completion Overrun
Split Request Delayed
Secondary Clock Frequency
Reserved
FUNCTION
Function Number
Device Number
Bus Number
64-bit Device on Primary
Bus Interface
133MHz Capable
TYPE
TYPE
RWC
RWC
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
When this bit is set to 1, a split completion has been terminated by
PI7C9X110 with either a retry or disconnect at the next ADB due to the
buffer full condition
Reset to 0
When this bit is set to 1, a split request is delayed because PI7C9X110 is not
able to forward the split request transaction to its secondary bus due to
insufficient room within the limit specified in the split transaction
commitment limit field of the downstream split transaction control register
Reset to 0
These bits are only meaningful in forward bridge mode. In reverse bridge
mode, all three bits are set to zero.
000: Conventional PCI mode (minimum clock period not applicable)
001: 66MHz (minimum clock period is 15ns)
010: 100 to 133MHz (minimum clock period is 7.5ns)
011: Reserved
1xx: Reserved
Reset to 000
0000000
DESCRIPTION
Function number (AD [10:8] of a type 0 configuration transaction)
Reset to 000
Device number (AD [15:11] of a type 0 configuration transaction) is assigned
to the PI7C9X110 by the connection of system hardware. Each time the
PI7C9X110 is addressed by a configuration write transaction, the bridge
updates this register with the contents of AD [15:11] of the address phase of
the configuration transaction, regardless of which register in the PI7C9X110
is addressed by the transaction. The PI7C9X110 is addressed by a
configuration write transaction if all of the following are true:
•
•
•
•
Reset to 11111
Additional address from which the contents of the primary bus number
register on type 1 configuration space header is read. The PI7C9X110 uses
the bus number, device number, and function number fields to create a
completer ID when responding with a split completion to a read of an internal
PI7C9X110 register. These fields are also used for cases when one interface
is in conventional PCI mode and the other is in PCI-X mode.
Reset to 11111111
64-bit not supported
Reset to 0
When this bit is 1, PI7C9X110 is 133MHz capable on its primary bus
interface
Reset to 0 in forward bridge mode or 1 in reverse bridge mode
The transaction uses a configuration write command
IDSEL is asserted during the address phase
AD [1:0] are 00 (type o configuration transaction)
AD [10:8] of the configuration address contain the appropriate function
number
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110