PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 76

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.5
7.5.6
Pericom Semiconductor
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFSET 08h
BIT
24
26:25
27
28
29
30
31
BIT
7:0
FUNCTION
Master Data Parity Error
Detected
DEVSEL_L Timing
(medium decode)
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
FUNCTION
Revision
TYPE
TYPE
RWC
RWC
RWC
RWC
RWC
RWC
RO
RO
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DESCRIPTION
FORWARD BRIDGE –
•
•
REVERSE BRIDGE –
•
•
•
Reset to 0
These bits apply to reverse bridge only.
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 00 when forward bridge or 01 when reverse bridge.
FORWARD BRIDGE –
This bit is set when PI7C9X110 completes a request using completer abort
status on the primary
REVERSE BRIDGE –
This bit is set to indicate a target abort on the primary
Reset to 0
FORWARD BRIDGE –
This bit is set when bridge receives a completion with completer abort
completion status on the primary
REVERSE BRIDGE –
This bit is set when PI7C9X110 detects a target abort on the primary
Reset to 0
FORWARD BRIDGE –
This bit is set when PI7C9X110 receives a completion with unsupported
request completion status on the primary
REVERSE BRIDGE –
This bit is set when PI7C9X110 detects a master abort on the primary
FORWARD BRIDGE –
This bit is set when PI7C9X110 sends an ERR_FATAL or
ERR_NON_FATAL message on the primary
REVERSE BRIDGE –
This bit is set when PI7C9X110 asserts SERR_L on the primary
Reset to 0
FORWARD BRIDGE –
This bit is set when poisoned TLP is detected on the primary
REVERSE BRIDGE –
This bit is set when address or data parity error is detected on the primary
Reset to 0
DESCRIPTION
Reset to 00000002h
Bit set if its Parity Error Enable bit is set and either of the conditions occurs
Receives a completion marked poisoned
Poisons a write request
Detected parity error when receiving data or Split Response for read
Observes P_PERR_L asserted when sending data or receiving Split
Response for write
Receives a Split Completion Message indicating data parity error
occurred for non-posted write
on the primary:
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110