PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 9

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.6
7.5.95
7.5.96
7.5.97
7.5.98
7.5.99
7.5.100
7.5.101
7.5.102
7.5.103
7.5.104
7.5.105
7.5.106
7.5.107
7.5.108
7.5.109
7.5.110
7.5.111
7.5.112
7.5.113
7.5.114
7.5.115
7.5.116
7.5.117
7.5.118
7.5.119
7.5.120
7.5.121
7.5.122
7.5.123
7.5.124
7.5.125
7.5.126
7.5.127
7.5.128
7.5.129
7.5.130
7.5.131
7.5.132
7.5.133
7.5.134
7.5.135
7.5.136
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.6.7
7.6.8
7.6.9
Pericom Semiconductor
CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT BRIDGE MODE 124
UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET E8h ....................... 114
UPSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ECh............................................. 114
MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h............................................................. 116
NEXT CAPABILITIES POINTER REGISTER – F0h.......................................................................... 116
MESSAGE CONTROL REGISTER – OFFSET F0h ........................................................................... 116
MESSAGE ADDRESS REGISTER – OFFSET F4h ............................................................................ 116
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h............................................................... 116
MESSAGE DATA REGISTER – OFFSET FCh................................................................................... 116
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h ............................ 117
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h ................ 117
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h .............................................................. 117
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 117
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 117
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch............................................. 118
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h....................................................... 118
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h .......................................................... 118
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h...................... 119
HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................. 119
HEADER LOG REGISTER 2 – OFFSET 120h................................................................................... 119
HEADER LOG REGISTER 3 – OFFSET 124h................................................................................... 119
HEADER LOG REGISTER 4 – OFFSET 128h................................................................................... 119
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ......................... 119
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................. 120
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ...................... 120
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h........................ 121
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................. 121
RESERVED REGISTER – OFFSET 14Ch .......................................................................................... 121
VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................. 121
VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................. 121
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h .............................................................. 122
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h .................................................................... 122
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h .................................................................... 122
PORT VC CONTROL REGISTER – OFFSET 15Ch........................................................................... 122
PORT VC STATUS REGISTER – OFFSET 15Ch............................................................................... 122
VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ........................................................... 122
VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ............................................................... 122
VC0 RESOURCE STATUS REGISTER – OFFSET 168h ................................................................... 123
RESERVED REGISTERS – OFFSET 16Ch – 300h ............................................................................ 123
EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h........................................... 123
RESERVED REGISTERS – OFFSET 308h – 30Ch ............................................................................ 123
REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ........................................... 123
RESERVED REGISTERS – OFFSET 314h – FFCh ........................................................................... 123
RESERVED REGISTERS – OFFSET 000h TO 004h.......................................................................... 124
DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER – OFFSET 008h ............................ 124
DOWNSTREAM MEMORY 2 SETUP REGISTER – OFFSET 00Ch.................................................. 124
DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER – OFFSET 010h ............................ 124
DOWNSTREAM MEMORY 3 SETUP REGISTER – OFFSET 014h .................................................. 125
DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 018h ........................ 125
RESERVED REGISTERS – OFFSET 01Ch TO 030h ......................................................................... 125
UPSTREAM MEMORY 3 SETUP REGISTER – OFFSET 34h........................................................... 125
UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 038h............................... 126
Page 9 of 145
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110