PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 7

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

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Pericom Semiconductor
PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT BRIDGE MODE ...... 74
PORT VC STATUS REGISTER – OFFSET 15Ch................................................................................. 72
VC0 RESOURCE CAPABILITY REGISTER – OFFSET 160h ............................................................. 72
VC0 RESOURCE CONTROL REGISTER – OFFSET 164h ................................................................. 72
VC0 RESOURCE STATUS REGISTER – OFFSET 168h ..................................................................... 73
RESERVED REGISTERS – OFFSET 16Ch – 300h .............................................................................. 73
EXTRA GPI/GPO DATA AND CONTROL REGISTER – OFFSET 304h............................................. 73
RESERVED REGISTERS – OFFSET 308h – 30Ch .............................................................................. 73
REPLAY AND ACKNOWLEDGE LATENCY TIMERS – OFFSET 310h ............................................. 73
RESERVED REGISTERS – OFFSET 314h – FFCh ............................................................................. 73
VENDOR ID – OFFSET 00h ................................................................................................................ 74
DEVICE ID – OFFSET 00h.................................................................................................................. 74
COMMAND REGISTER – OFFSET 04h .............................................................................................. 74
PRIMARY STATUS REGISTER – OFFSET 04h................................................................................... 75
REVISION ID REGISTER – OFFSET 08h ........................................................................................... 76
CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 76
CACHE LINE SIZE REGISTER – OFFSET 0Ch.................................................................................. 77
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 77
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 77
PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 10h................................ 77
PRIMARY CSR I/O BASE ADDRESS REGISTER – OFFSET 14h ....................................................... 78
DOWNSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 18h .......................... 78
DONWSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 1Ch ...................................... 79
DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 20h....................................... 79
DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 24h ......................... 80
RESERVED REGISTER – OFFSET 28h............................................................................................... 80
SUBSYTEM ID AND SUBSYSTEM VENDOR ID REGISTER – OFFSET 2Ch.................................... 80
RESERVED REGISTER – OFFSET 30h............................................................................................... 80
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 80
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 80
PRIMARY INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................. 80
PRIMARY INTERRUPT PIN REGISTER – OFFSET 3Ch.................................................................... 80
PRIMARY MINIMUM GRANT REGISTER – OFFSET 3Ch ................................................................ 81
PRIMARY MAXIMUM LATENCY TIME REGISTER – OFFSET 3Ch................................................. 82
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 82
CHIP CONTROL 0 REGISTER – OFFSET 40h................................................................................... 83
SECONDARY COMMAND REGISTER – OFFSET 44h ...................................................................... 84
SECONDARY STATUS REGISTER – OFFSET 44h............................................................................. 85
ARBITER ENABLE REGISTER – OFFSET 48h................................................................................... 87
ARBITER MODE REGISTER – OFFSET 48h...................................................................................... 87
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 88
SECONDARY CACHE LINE SIZE REGISTER – OFFSET 4Ch .......................................................... 89
SECONDARY LATENCY TIME REGISTER – OFFSET 4Ch............................................................... 89
SECONDARY HEADER TYPE REGISTER – OFFSET 4Ch ................................................................ 89
SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 50h.......................... 89
SECONDARY CSR I/O BASE ADDRESS REGISTER – OFFSET 54h ................................................. 90
UPSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 58h................................. 90
UPSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 5Ch............................................. 91
UPSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 60h ............................................. 91
UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 64h................................ 93
EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h.................................................... 93
MEMORY ADDRESS FORWARDING CONTROL REGISTER – OFFSET 68h .................................. 94
Page 7 of 145
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110