PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 101

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.61 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h
7.5.62 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h
7.5.63 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h
Pericom Semiconductor
BIT
15:8
BIT
18:16
19
20
21
24:22
25
26
31:27
BIT
1:0
7:2
FUNCTION
Next Pointer
FUNCTION
Version Number
PME Clock
Reserved
Device Specific Initialization
(DSI)
AUX Current
D1 Power Management
D2 Power Management
PME_L Support
FUNCTION
Power State
Reserved
TYPE
TYPE
TYPE
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Next pointer (point to Subsystem ID and Subsystem Vendor ID)
Reset to A8h
DESCRIPTION
Version number that complies with revision 2.0 of the PCI Power
Management Interface specification.
Reset to 010
PME clock is not required for PME_L generation
Reset to 0
Reset to 0
DSI – no special initialization of this function beyond the standard PCI
configuration header is required following transition to the D0 un-initialized
state
Reset to 0
000: 0mA
001: 55mA
010: 100mA
011: 160mA
100: 220mA
101: 270mA
110: 320mA
111: 375mA
Reset to 001
D1 power management is not supported
Reset to 0
D2 power management is not supported
Reset to 0
PME_L is supported in D3 cold, D3 hot, and D0 states.
Reset to 11001
DESCRIPTION
Power State is used to determine the current power state of PI7C9X110. If a
non-implemented state is written to this register, PI7C9X110 will ignore the
write data. When present state is D3 and changing to D0 state by
programming this register, the power state change causes a device reset
without activating the RESET_L of PCI/PCI-X bus interface
00: D0 state
01: D1 state not implemented
10: D2 state not implemented
11: D3 state
Reset to 00
Reset to 000000
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110