PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 34

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.4.4
Pericom Semiconductor
PRIMARY STATUS REGISTER – OFFSET 04h
BIT
9
10
15:11
BIT
18:16
19
20
21
22
23
24
26:25
27
28
FUNCTION
Fast Back-to-Back Enable
Interrupt Disable
Reserved
FUNCTION
Reserved
Reserved (transparent mode)
Capability List Capable
66MHz Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
Detected
DEVSEL_L Timing
(medium decode)
Signaled Target Abort
Received Target Abort
RO
RO
RO
RWC
RO
RWC
RWC
TYPE
TYPE
RO /
RW
RO
RO
RO
RO
RO
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DESCRIPTION
SERR_L on the primary interface
Reset to 0
Fast back-to-back enable not supported
Reset to 0
This bit applies to reverse bridge only.
0: INTA_L, INTB_L, INTC_L, and INTD_L can be asserted on PCI
interface
1: Prevent INTA_L, INTB_L, INTC_L, and INTD_L from being asserted on
PCI interface
Reset to 0
Reset to 00000
DESCRIPTION
Reset to 000
Reset to 0
1: PI7C9X110 supports the capability list (offset 34h in the pointer to the
data structure)
Reset to 1
This bit applies to reverse bridge only.
1: 66MHz capable
Reset to 0 when forward bridge or 1 when reverse bridge.
Reset to 0
This bit applies to reverse bridge only.
1: Enable fast back-to-back transactions
Reset to 0 when forward bridge or 1 when reverse bridge in PCI mode.
Bit set if its Parity Error Enable bit is set and either of the conditions occurs
on the primary:
FORWARD BRIDGE –
Receives a completion marked poisoned
Poisons a write request
REVERSE BRIDGE –
Detected parity error when receiving data or Split Response for read
Observes P_PERR_L asserted when sending data or receiving Split Response
for write
Receives a Split Completion Message indicating data parity error occurred
for non-posted write
Reset to 0
These bits apply to reverse bridge only.
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 00 when forward bridge or 01 when reverse bridge.
FORWARD BRIDGE –
This bit is set when PI7C9X110 completes a request using completer abort
status on the primary
REVERSE BRIDGE –
This bit is set to indicate a target abort on the primary
Reset to 0
FORWARD BRIDGE –
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110