PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 79

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.13 DONWSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 1Ch
7.5.14 DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 20h
Pericom Semiconductor
BIT
BIT
0
2:1
3
11:4
31:12
BIT
0
2:1
3
11:4
31:12
FUNCTION
FUNCTION
Space Indicator
Address Type
Prefetchable control
Reserved
Base Address
FUNCTION
Space Indicator
Address Type
Prefetchable control
Reserved
Base Address
RW/RO
RW/RO
TYPE
TYPE
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
Page 79 of 145
DESCRIPTION
setup register is set to one, then the correspondent bit of this register will be
changed to RW.
Reset to 00000h
DESCRIPTION
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01, 10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from
Downstream Memory 2 Setup Register (CSR Offset 00Ch), which can be
initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero
to bit [31] of the setup register to disable this register. The range of this
register is from 4KB to 2GB for memory space. PI7X9X110 uses
downstream Memory 2 Translated Base Register (CSR Offset 008h) to
formulate direct address translation. If a bit in the setup register is set to one,
then the correspondent bit of this register will be changed to RW.
Reset to 00000h
DESCRIPTION
0: Memory space
1: IO space
Reset to 0
00: 32-bit address decode range
01: 64-bit address decode range
10 and 11: reserved
Reset to 00
0: Memory space is non-prefetchable
1: Memory space is prefetchable
Reset to 0
Reset to 0
The size and type of this Base Address Register are defined from
Downstream Memory 3 Setup Register (CSR Offset 014h), which can be
initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero
to bit [31] of the setup registers (CSR Offset 014h and 018h) to disable this
register. The range of this register is from 4KB to 9EB for memory space.
PI7C9X110 uses Memory 3 Translated Base Register (CSR Offset 010h) to
formulate direct address translation when 32-bit addressing programmed.
When 64-bit addressing programmed, no address translation is performed. If
a bit in the setup register is set to one, then the correspondent bit of this
register will be changed to RW.
Reset to 00000h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110