PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 84

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.27 SECONDARY COMMAND REGISTER – OFFSET 44h
Pericom Semiconductor
BIT
20
22:21
23
25:24
26
29:27
30
31
BIT
0
1
FUNCTION
PCI Discard Timer Short
Duration
Configuration Request Retry
Timer Counter Value
Control
Delayed Transaction Order
Control
Completion Timer Counter
Value Control
Isochronous Traffic Support
Enable
Traffic Class Used For
Isochronous Traffic
Serial Link Interface
Loopback Enable
Primary Configuration
Access Lockout
FUNCTION
I/O Space Enable
Memory Space Enable
TYPE
TYPE
RW /
RO /
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
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DESCRIPTION
0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for
reverse bridge to indicate how many PCI clocks should be allowed before the
PCI discard timer expires
1: 64 PCI clocks allowed before the PCI discard timer expires
Reset to 0
00: Timer expires at 25us
01: Timer expires at 0.5ms
10: Timer expires at 5ms
11: Timer expires at 25ms
Reset to 01
0: Enable out-of-order capability between delayed transactions
1: Disable out-of-order capability between delayed transactions
Reset to 0
00: Timer expires at 50us
01: Timer expires at 10ms
10: Timer expires at 50ms
11: Timer disabled
Reset to 01
0: All memory transactions from PCI-X to PCIe will be mapped to TC0
1: All memory transactions from PCI-X to PCIe will be mapped to Traffic
Class defined in bit [29:27] of offset 40h.
Reset to 0
Reset to 001
0: Normal mode
1: Enable serial link interface loopback mode (TX to RX) if TM0=LOW,
TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. PCI
transaction from PCI bus will loop back to PCI bus
RO for forward bridge
Reset to 0
0: PI7C9X110 configuration space can be accessed from both interfaces
1: PI7C9X110 configuration space can only be accessed from the secondary
interface. Primary bus accessed receives completion with CRS status for
forward bridge, or target retry for reverse bridge
Reset to 0 if TM0 is LOW
DESCRIPTION
0: Ignore I/O transactions on the secondary interface
1: Enable response to memory transactions on the secondary interface
Reset to 0
0: Ignore memory read transactions on the secondary interface
1: Enable memory read transactions on the secondary interface
Reset to 0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110