PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 114

no-image

PI7C9X110

Manufacturer Part Number
PI7C9X110
Description
Pcie-to-pci Reversible Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C9X110BNB
Manufacturer:
LATTICE
Quantity:
308
Part Number:
PI7C9X110BNB
Manufacturer:
PERICOM
Quantity:
20 000
Part Number:
PI7C9X110BNBE
Manufacturer:
PLX
Quantity:
1 238
Part Number:
PI7C9X110BNBE
Manufacturer:
PERICOM31
Quantity:
193
Part Number:
PI7C9X110BNBE
Manufacturer:
Pericom
Quantity:
10 000
Part Number:
PI7C9X110BNBE
Manufacturer:
PERICOM
Quantity:
20 000
Part Number:
PI7C9X110BNBE
0
7.5.94 UPSTREAM MEMORY 0 SETUP REGISTER – OFFSET E4h
7.5.95 UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET E8h
7.5.96 UPSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ECh
Pericom Semiconductor
BIT
0
2:1
3
11:4
30:12
31
BIT
5:0
31:6
BIT
0
2:1
3
5:4
30:6
FUNCTION
Type Selector
Address Type
Prefetchable Control
Reserved
Base Address Register Size
Base Address Register
Enable
FUNCTION
Reserved
Upstream I/O or Memory 1
Translated Base
FUNCTION
Type Selector
Address Type
Prefetchable Control
Reserved
Base Address Register Size
TYPE
TYPE
TYPE
(WS)
(WS)
(WS)
(WS)
(WS)
(WS)
(WS)
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 114 of 145
DESCRIPTION
0: Memory space is requested
Reset to 0
00: 32-bit address space
01: 64-bit address space
Reset to 00
0: Non-prefetchable
1: Prefetchable
Reset to 0
Reset to 00h
0: Set the corresponding bit in the Base Address Register to read only.
1: Set the corresponding bit in the Base Address Register to read/write in
order to control the size of the address range.
Reset to 00000h
Always set to 1 when a bus master attempts to write a zero to this bit.
PI7C9X110 returns bit [31:12] as FFFFFh (for 4KB size).
Reset to 1
DESCRIPTION
Reset to 000000
Define the translated base address for upstream I/O or memory transactions
whose initiator addresses fall into Upstream I/O or Memory 1 address range.
The number of bits that are used for translated base is determined by its setup
register (offset ECh)
Reset to 00000h
DESCRIPTION
0: Memory space is requested
Reset to 0
00: 32-bit address space
01: 64-bit address space
Reset to 00
0: Non-prefetchable
1: Prefetchable
Reset to 0
Reset to 00
0: Set the corresponding bit in the Base Address Register to read only.
1: Set the corresponding bit in the Base Address Register to read/write in
order to control the size of the address range. If memory space is selected,
bit [11:6] should be set to zeros.
Reset to 00000000h
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110

Related parts for PI7C9X110