PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet - Page 96

• Manufacturer Part Number: PI7C9X110
• Description: Pcie-to-pci Reversible Bridge
• Manufacturer: Pericom Semiconductor Corporation

7.5.47 RESERVED REGISTER – OFFSET 74h
7.5.48 BRIDGE CONTROL AND STATUS REGISTER – OFFSET 78h
Pericom Semiconductor
BIT
7
8
15:9
31:16
BIT
1:0
2
3
5:4
6
7
8
FUNCTION
Fast EEPROM Autoload
Control
EEPROM Autoload Status
EEPROM Word Address
EEPROM Data
FUNCTION
Reserved
SERR_L Forward Enable
Secondary Interface Reset
VGA Enable
VGA 16-bit Decode
Master Abort Mode
Primary Master Timeout
RO
RW/RO
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RO
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DESCRIPTION
0: Normal speed of EEPROM autoload
1: Increase EEPROM autoload by 32x
Reset to 0
0: EEPROM autoload is not on going
1: EEPROM autoload is on going
Reset to 0
EEPROM word address for EEPROM cycle
Reset to 0000000
EEPROM data to be written into the EEPROM
Reset to 0000h
DESCRIPTION
Reset to 00
0: Disable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
1: Enable the forwarding of SERR_L to ERR_FATAL and
ERR_NONFATAL
Reset to 0 (FORWARD BRIDGE)
RO bit for REVERSE BRIDGE
0: Do not force the assertion of RESET_L on secondary PCI/PCI-X bus in
forward bridge mode, or do not generate a hot reset on the PCI Express link
in reverse bridge mode
1: Force the assertion of RESET_L on secondary PCI/PCI-X bus in forward
bridge mode, or generate a hot reset on the PCI Express link in reverse bridge
mode
Reset to 0
00: VGA memory and I/O transactions on the primary and secondary
interfaces are ignored, unless decoded by other mechanism
01: VGA memory and I/O transactions on the primary interface are
forwarded to secondary interface without address translation, but VGA
transactions on secondary interface are ignored
10: VGA memory and I/O transactions on the secondary interface are
forwarded to primary interface without address translation, but VGA
transactions on primary interface are ignored
Reset to 00
0: Execute 10-bit address decodes on VGA I/O accesses
1: Execute 16-bit address decode on VGA I/O accesses
Reset to 0
0: Do not report master aborts (return FFFFFFFFh on reads and discards
data on write)
1: Report master abort by signaling target abort if possible or by the
assertion of SERR_L (if enabled).
Reset to 0
0: Primary discard timer counts 215 PCI clock cycles
1: Primary discard timer counts 210 PCI clock cycles
FORWARD BRIDGE – Bit is RO and ignored by PI7C9X110
Reset to 0
May 2008, Revision 2.6
PCIe-to-PCI Reversible Bridge
PI7C9X110