ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 125

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Watchdog Timer Registers
Table 47. WDT Approximate Time-Out Delays for Possible Clock Sources
RESET or NMI Generation
A WDT time-out causes a RESET or sends a NMI signal to the CPU. The default opera-
tion is for the WDT to cause a RESET.
If the NMI_OUT bit in the WDT_CTL register is set to 0, then on a WDT time-out, the
RST_FLAG bit in the WDT_CTL register is set to 1. The RST_FLAG bit is polled by the
CPU to determine the source of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then on time-out, the WDT
asserts an NMI for CPU processing. The NMI_FLAG bit is polled by the CPU to deter-
mine the source of the NMI event.
Watchdog Timer Control Register
The Watchdog Timer Control register (see
Read/Write register used to enable the Watchdog Timer, set the time-out period, indicate
the source of the most recent RESET or NMI, and select the required operation on WDT
time-out.
The default clock source for the WDT is the WDT oscillator (WDT_CLK =
To power-down the WDT oscillator, another clock source must be selected. The power-
up sequence of the WDT oscillator takes approximately 20 ms.
WDT_CLK[
3:2]
WDT_PERI
OD[1:0]
00
01
10
11
Divider Timeout
50 MHz system
2
2
2
2
27
25
22
18
clock
00
83.9 ms
5.2 ms
2.68 s
0.67 s
Divider
32.768 kHz RTC
2
2
2
2
17
14
11
7
clock
01
Table 48
Timeout Divider Timeout Divider Timeout
62.5 ms
3.9 ms
4.00 s
0.5 s
) is an 8-bit
oscillator (~10
2
2
2
2
Internal RC
15
13
9
5
kHz)
10
51.2 ms
3.2 ms
3.28 s
0.82 s
Product Specification
eZ80F91 ASSP
-
-
-
-
Reserved
Watchdog Timer
10b
11
).
-
-
-
-
117