ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 78

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
ADDR[23:0]
DATA[7:0]
Chip Selects During Bus Request/Bus Acknowledge Cycles
Bus Mode Controller
INSTRD
(output)
MREQ
SCLK
CSx
RD
When the CPU relinquishes the address bus to an external peripheral in response to an
external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The
external peripheral then drives the address bus (and data bus). The CPU continues to gen-
erate chip select signals in response to the address on the bus. External devices cannot
access the internal registers of the eZ80F91.
The bus mode controller allows the address and data bus timing and signal formats of the
eZ80F91 to be configured to connect with external devices compatible with eZ80
Z80(®), Intel™ and Motorola microcontrollers. Bus modes for each of the chip selects are
configured independently using the Chip Select Bus Mode Control Registers. The number
Figure 9. Example: Wait State Read Operation
T
CLK
T
WAIT
Chip Selects and Wait States
Product Specification
eZ80F91 ASSP
®
,
70