ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 314

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 184. EMAC Configuration Register 3
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
LONGP
6
PUREP
5
XSDFR
4
BITMD
[3:0]
RETRY
Note: IEEE 802.3 specifies a minimum of 56 bits of preamble. A maximum number of bits is not de-
fined. For details, see the IEEE 802.3 Specification, Section 7.2.3.2.
EMAC Configuration Register 3
The EMAC Configuration Register 3 controls preamble length and value, excessive defer-
ment, and the number of retransmission tries. See
Value
0
1
0
1
0
1
0
1
0h–Fh
R/W
Description
The EMAC allows any preamble length as per the IEEE 802.3
specification.*
The EMAC only allows Receive packets that contain preamble
fields less than 12 bytes in length.*
No preamble error checking is performed.
The EMAC verifies the content of the preamble to ensure that it
contains a value of 55h and that it is error-free. Packets
containing an errored preamble are discarded.
The EMAC aborts when the excessive deferral limit is reached.
The EMAC defers to the carrier indefinitely as per the IEEE
802.3 specification.
Disable 10 Mbps ENDEC mode.
Enable 10 Mbps ENDEC mode.
A programmable field specifying the number of retransmission
attempts following a collision before aborting the packet due to
excessive collisions.
7
0
R/W
6
0
R/W
5
0
(EMAC_CFG3 = 0023h)
R/W
4
0
R/W
3
1
Table
R/W
2
1
184.
R/W
Ethernet Media Access Controller
1
1
Product Specification
R/W
0
1
eZ80F91 ASSP
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